VxWorks API Reference : OS Libraries
pentiumALib - P5, P6 and P7 family processor specific routines
pentiumCr4Get( ) - get contents of CR4 register
pentiumCr4Set( ) - sets specified value to the CR4 register
pentiumP6PmcStart( ) - start both PMC0 and PMC1
pentiumP6PmcStop( ) - stop both PMC0 and PMC1
pentiumP6PmcStop1( ) - stop PMC1
pentiumP6PmcGet( ) - get the contents of PMC0 and PMC1
pentiumP6PmcGet0( ) - get the contents of PMC0
pentiumP6PmcGet1( ) - get the contents of PMC1
pentiumP6PmcReset( ) - reset both PMC0 and PMC1
pentiumP6PmcReset0( ) - reset PMC0
pentiumP6PmcReset1( ) - reset PMC1
pentiumP5PmcStart0( ) - start PMC0
pentiumP5PmcStart1( ) - start PMC1
pentiumP5PmcStop( ) - stop both P5 PMC0 and PMC1
pentiumP5PmcStop0( ) - stop P5 PMC0
pentiumP5PmcStop1( ) - stop P5 PMC1
pentiumP5PmcGet( ) - get the contents of P5 PMC0 and PMC1
pentiumP5PmcGet0( ) - get the contents of P5 PMC0
pentiumP5PmcGet1( ) - get the contents of P5 PMC1
pentiumP5PmcReset( ) - reset both PMC0 and PMC1
pentiumP5PmcReset0( ) - reset PMC0
pentiumP5PmcReset1( ) - reset PMC1
pentiumTscGet64( ) - get 64Bit TSC (Timestamp Counter)
pentiumTscGet32( ) - get the lower half of the 64Bit TSC (Timestamp Counter)
pentiumTscReset( ) - reset the TSC (Timestamp Counter)
pentiumMsrGet( ) - get the contents of the specified MSR (Model Specific Register)
pentiumMsrSet( ) - set a value to the specified MSR (Model Specific Registers)
pentiumTlbFlush( ) - flush TLBs (Translation Lookaside Buffers)
pentiumSerialize( ) - execute a serializing instruction CPUID
pentiumBts( ) - execute atomic compare-and-exchange instruction to set a bit
pentiumBtc( ) - execute atomic compare-and-exchange instruction to clear a bit
This module contains Pentium and PentiumPro specific routines written in assembly language.
The Pentium processor introduced a new exception called the machine-check exception (interrupt-18). This exception is used to signal hardware-related errors, such as a parity error on a read cycle. The PentiumPro processor extends the types of errors that can be detected and that generate a machine- check exception. It also provides a new machine-check architecture that records information about a machine-check error and provides the basis for an extended error logging capability.MCA is enabled and its status registers are cleared zero in sysHwInit( ). Its registers are accessed by pentiumMsrSet( ) and pentiumMsrGet( ).
The P5 and P6 family of processor has two performance-monitoring counters for use in monitoring internal hardware operations. These counters are duration or event counters that can be programmed to count any of approximately 100 different types of events, such as the number of instructions decoded, number of interrupts received, or number of cache loads. However, the set of events can be counted with PMC is different in the P5 and P6 family of processors; and the locations and bit difinitions of the related counter and control registers are also different. So there are two set of PMC routines, one for P6 family and one for p5 family respectively.There are nine routines to interface the PMC of P6 family processors. These nine routines are:
STATUS pentiumP6PmcStart ( int pmcEvtSel0; /* performance event select register 0 */ int pmcEvtSel1; /* performance event select register 1 */ ) void pentiumP6PmcStop (void) void pentiumP6PmcStop1 (void) void pentiumP6PmcGet ( long long int * pPmc0; /* performance monitoring counter 0 */ long long int * pPmc1; /* performance monitoring counter 1 */ ) void pentiumP6PmcGet0 ( long long int * pPmc0; /* performance monitoring counter 0 */ ) void pentiumP6PmcGet1 ( long long int * pPmc1; /* performance monitoring counter 1 */ ) void pentiumP6PmcReset (void) void pentiumP6PmcReset0 (void) void pentiumP6PmcReset1 (void)pentiumP6PmcStart( ) starts both PMC0 and PMC1. pentiumP6PmcStop( ) stops them, and pentiumP6PmcStop1( ) stops only PMC1. pentiumP6PmcGet( ) gets contents of PMC0 and PMC1. pentiumP6PmcGet0( ) gets contents of PMC0, and pentiumP6PmcGet1( ) gets contents of PMC1. pentiumP6PmcReset( ) resets both PMC0 and PMC1. pentiumP6PmcReset0( ) resets PMC0, and pentiumP6PmcReset1( ) resets PMC1. PMC is enabled in sysHwInit( ). Selected events in the default configuration are PMC0 = number of hardware interrupts received and PMC1 = number of misaligned data memory references.There are ten routines to interface the PMC of P5 family processors. These ten routines are:
STATUS pentiumP5PmcStart0 ( int pmc0Cesr; /* PMC0 control and event select */ ) STATUS pentiumP5PmcStart1 ( int pmc1Cesr; /* PMC1 control and event select */ ) void pentiumP5PmcStop0 (void) void pentiumP5PmcStop1 (void) void pentiumP5PmcGet ( long long int * pPmc0; /* performance monitoring counter 0 */ long long int * pPmc1; /* performance monitoring counter 1 */ ) void pentiumP5PmcGet0 ( long long int * pPmc0; /* performance monitoring counter 0 */ ) void pentiumP5PmcGet1 ( long long int * pPmc1; /* performance monitoring counter 1 */ ) void pentiumP5PmcReset (void) void pentiumP5PmcReset0 (void) void pentiumP5PmcReset1 (void)pentiumP5PmcStart0( ) starts PMC0, and pentiumP5PmcStart1( ) starts PMC1. pentiumP5PmcStop0( ) stops PMC0, and pentiumP5PmcStop1( ) stops PMC1. pentiumP5PmcGet( ) gets contents of PMC0 and PMC1. pentiumP5PmcGet0( ) gets contents of PMC0, and pentiumP5PmcGet1( ) gets contents of PMC1. pentiumP5PmcReset( ) resets both PMC0 and PMC1. pentiumP5PmcReset0( ) resets PMC0, and pentiumP5PmcReset1( ) resets PMC1. PMC is enabled in sysHwInit( ). Selected events in the default configuration are PMC0 = number of hardware interrupts received and PMC1 = number of misaligned data memory references.
The concept of model-specific registers (MSRs) to control hardware functions in the processor or to monitor processor activity was introduced in the PentiumPro processor. The new registers control the debug extensions, the performance counters, the machine-check exception capability, the machine check architecture, and the MTRRs. The MSRs can be read and written to using the RDMSR and WRMSR instructions, respectively.There are two routines to interface the MSR. These two routines are:
void pentiumMsrGet ( int address, /* MSR address */ long long int * pData /* MSR data */ ) void pentiumMsrSet ( int address, /* MSR address */ long long int * pData /* MSR data */ )pentiumMsrGet( ) get contents of the specified MSR, and pentiumMsrSet( ) sets value to the specified MSR.
The PentiumPro processor provides a 64-bit time-stamp counter that is incremented every processor clock cycle. The counter is incremented even when the processor is halted by the HLT instruction or the external STPCLK# pin. The time-stamp counter is set to 0 following a hardware reset of the processor. The RDTSC instruction reads the time stamp counter and is guaranteed to return a monotonically increasing unique value whenever executed, except for 64-bit counter wraparound. Intel guarantees, architecturally, that the time-stamp counter frequency and configuration will be such that it will not wraparound within 10 years after being reset to 0. The period for counter wrap is several thousands of years in the PentiumPro and Pentium processors.There are three routines to interface the TSC. These three routines are:
void pentiumTscReset (void) void pentiumTscGet32 (void) void pentiumTscGet64 ( long long int * pTsc /* TSC */ )pentiumTscReset( ) resets the TSC. pentiumTscGet32( ) gets the lower half of the 64Bit TSC, and pentiumTscGet64( ) gets the entire 64Bit TSC.Four other routines are provided in this library. They are:
void pentiumTlbFlush (void) void pentiumSerialize (void) STATUS pentiumBts ( char * pFlag /* flag address */ ) STATUS pentiumBtc (pFlag) ( char * pFlag /* flag address */ )pentiumTlbFlush( ) flushes TLBs (Translation Lookaside Buffers). pentiumSerialize( ) does serialization by executing CPUID instruction. pentiumBts( ) executes an atomic compare-and-exchange instruction to set a bit. pentiumBtc( ) executes an atomic compare-and-exchange instruction to clear a bit.
Pentium, PentiumPro Family Developer's Manual
pentiumCr4Get( ) - get contents of CR4 register
int pentiumCr4Get (void)
This routine gets the contents of the CR4 register. This routine is kept for the backward compatibility, and vxCr4Get( ) should be used instead. The CR4 is introduced in the Pentium processor, thus this routine just returns in the pre Pentium generation processors.
Contents of CR4 register.
pentiumCr4Set( ) - sets specified value to the CR4 register
void pentiumCr4Set (cr4) int cr4; /* value to write CR4 register */
This routine sets a specified value to the CR4 register. This routine is kept for the backward compatibility, and vxCr4Set( ) should be used instead. The CR4 is introduced in the Pentium processor, thus this routine just returns in the pre Pentium generation processors.
N/A
pentiumP6PmcStart( ) - start both PMC0 and PMC1
STATUS pentiumP6PmcStart (pmcEvtSel0, pmcEvtSel1) int pmcEvtSel0; /* Performance Event Select Register 0 */ int pmcEvtSel1; /* Performance Event Select Register 1 */
This routine starts both PMC0 (Performance Monitoring Counter 0) and PMC1 by writing specified events to Performance Event Select Registers. The first parameter is a content of Performance Event Select Register 0, and the second parameter is for the Performance Event Select Register 1.
OK or ERROR if PMC is already started.
pentiumP6PmcStop( ) - stop both PMC0 and PMC1
void pentiumP6PmcStop (void)
This routine stops both PMC0 (Performance Monitoring Counter 0) and PMC1 by clearing two Performance Event Select Registers.
N/A
pentiumP6PmcStop1( ) - stop PMC1
void pentiumP6PmcStop1 (void)
This routine stops only PMC1 (Performance Monitoring Counter 1) by clearing the Performance Event Select Register 1. Note, clearing the Performance Event Select Register 0 stops both counters, PMC0 and PMC1.
N/A
pentiumP6PmcGet( ) - get the contents of PMC0 and PMC1
void pentiumP6PmcGet (pPmc0, pPmc1) long long int * pPmc0; /* Performance Monitoring Counter 0 */ long long int * pPmc1; /* Performance Monitoring Counter 1 */
This routine gets the contents of both PMC0 (Performance Monitoring Counter 0) and PMC1. The first parameter is a pointer of 64Bit variable to store the content of the Counter 0, and the second parameter is for the Counter 1.
N/A
pentiumP6PmcGet0( ) - get the contents of PMC0
void pentiumP6PmcGet0 (pPmc0) long long int * pPmc0; /* Performance Monitoring Counter 0 */
This routine gets the contents of PMC0 (Performance Monitoring Counter 0). The parameter is a pointer of 64Bit variable to store the content of the Counter.
N/A
pentiumP6PmcGet1( ) - get the contents of PMC1
void pentiumP6PmcGet1 (pPmc1) long long int * pPmc1; /* Performance Monitoring Counter 1 */
This routine gets a content of PMC1 (Performance Monitoring Counter 1). Parameter is a pointer of 64Bit variable to store the content of the Counter.
N/A
pentiumP6PmcReset( ) - reset both PMC0 and PMC1
void pentiumP6PmcReset (void)
This routine resets both PMC0 (Performance Monitoring Counter 0) and PMC1.
N/A
pentiumP6PmcReset0( ) - reset PMC0
void pentiumP6PmcReset0 (void)
This routine resets PMC0 (Performance Monitoring Counter 0).
N/A
pentiumP6PmcReset1( ) - reset PMC1
void pentiumP6PmcReset1 (void)
This routine resets PMC1 (Performance Monitoring Counter 1).
N/A
pentiumP5PmcStart0( ) - start PMC0
STATUS pentiumP5PmcStart0 (pmc0Cesr) int pmc0Cesr; /* PMC0 control and event select */
This routine starts PMC0 (Performance Monitoring Counter 0) by writing specified PMC0 events to Performance Event Select Registers. The only parameter is the content of Performance Event Select Register.
OK or ERROR if PMC0 is already started.
pentiumP5PmcStart1( ) - start PMC1
STATUS pentiumP5PmcStart1 (pmc1Cesr) int pmc1Cesr; /* PMC1 control and event select */
This routine starts PMC1 (Performance Monitoring Counter 0) by writing specified PMC1 events to Performance Event Select Registers. The only parameter is the content of Performance Event Select Register.
OK or ERROR if PMC1 is already started.
pentiumP5PmcStop( ) - stop both P5 PMC0 and PMC1
void pentiumP5PmcStop (void)
This routine stops both PMC0 (Performance Monitoring Counter 0) and PMC1 by clearing two Performance Event Select Registers.
N/A
pentiumP5PmcStop0( ) - stop P5 PMC0
void pentiumP5PmcStop0 (void)
This routine stops only PMC0 (Performance Monitoring Counter 0) by clearing the PMC0 bits of Control and Event Select Register.
N/A
pentiumP5PmcStop1( ) - stop P5 PMC1
void pentiumP5PmcStop1 (void)
This routine stops only PMC1 (Performance Monitoring Counter 1) by clearing the PMC1 bits of Control and Event Select Register.
N/A
pentiumP5PmcGet( ) - get the contents of P5 PMC0 and PMC1
void pentiumP5PmcGet (pPmc0, pPmc1) long long int * pPmc0; /* Performance Monitoring Counter 0 */ long long int * pPmc1; /* Performance Monitoring Counter 1 */
This routine gets the contents of both PMC0 (Performance Monitoring Counter 0) and PMC1. The first parameter is a pointer of 64Bit variable to store the content of the Counter 0, and the second parameter is for the Counter 1.
N/A
pentiumP5PmcGet0( ) - get the contents of P5 PMC0
void pentiumP5PmcGet0 (pPmc0) long long int * pPmc0; /* Performance Monitoring Counter 0 */
This routine gets the contents of PMC0 (Performance Monitoring Counter 0). The parameter is a pointer of 64Bit variable to store the content of the Counter.
N/A
pentiumP5PmcGet1( ) - get the contents of P5 PMC1
void pentiumP5PmcGet1 (pPmc1) long long int * pPmc1; /* Performance Monitoring Counter 1 */
This routine gets a content of PMC1 (Performance Monitoring Counter 1). Parameter is a pointer of 64Bit variable to store the content of the Counter.
N/A
pentiumP5PmcReset( ) - reset both PMC0 and PMC1
void pentiumP5PmcReset (void)
This routine resets both PMC0 (Performance Monitoring Counter 0) and PMC1.
N/A
pentiumP5PmcReset0( ) - reset PMC0
void pentiumP5PmcReset0 (void)
This routine resets PMC0 (Performance Monitoring Counter 0).
N/A
pentiumP5PmcReset1( ) - reset PMC1
void pentiumP5PmcReset1 (void)
This routine resets PMC1 (Performance Monitoring Counter 1).
N/A
pentiumTscGet64( ) - get 64Bit TSC (Timestamp Counter)
void pentiumTscGet64 (pTsc) long long int * pTsc; /* Timestamp Counter */
This routine gets 64Bit TSC by RDTSC instruction. Parameter is a pointer of 64Bit variable to store the content of the Counter.
N/A
pentiumTscGet32( ) - get the lower half of the 64Bit TSC (Timestamp Counter)
UINT32 pentiumTscGet32 (void)
This routine gets a lower half of the 64Bit TSC by RDTSC instruction. RDTSC instruction saves the lower 32Bit in EAX register, so this routine simply returns after executing RDTSC instruction.
Lower half of the 64Bit TSC (Timestamp Counter)
pentiumTscReset( ) - reset the TSC (Timestamp Counter)
void pentiumTscReset (void)
This routine resets the TSC by writing zero to the TSC with WRMSR instruction.
N/A
pentiumMsrGet( ) - get the contents of the specified MSR (Model Specific Register)
void pentiumMsrGet (addr, pData) int addr; /* MSR address */ long long int * pData; /* MSR data */
This routine gets the contents of the specified MSR. The first parameter is an address of the MSR. The second parameter is a pointer of 64Bit variable.
N/A
pentiumMsrSet( ) - set a value to the specified MSR (Model Specific Registers)
void pentiumMsrSet (addr, pData) int addr; /* MSR address */ long long int * pData; /* MSR data */
This routine sets a value to a specified MSR. The first parameter is an address of the MSR. The second parameter is a pointer of 64Bit variable.
N/A
pentiumTlbFlush( ) - flush TLBs (Translation Lookaside Buffers)
void pentiumTlbFlush (void)
This routine flushes TLBs by loading the CR3 register. All of the TLBs are automatically invalidated any time the CR3 register is loaded. The page global enable (PGE) flag in register CR4 and the global flag in a page-directory or page-table entry can be used to frequently used pages from being automatically invalidated in the TLBs on a load of CR3 register. The only way to deterministically invalidate global page entries is to clear the PGE flag and then invalidate the TLBs.
N/A
pentiumSerialize( ) - execute a serializing instruction CPUID
void pentiumSerialize (void)
This routine executes a serializing instruction CPUID. Serialization means that all modifications to flags, registers, and memory by previous instructions are completed before the next instruction is fetched and executed and all buffered writes have drained to memory.
N/A
pentiumBts( ) - execute atomic compare-and-exchange instruction to set a bit
STATUS pentiumBts (pFlag) char * pFlag; /* flag address */
This routine compares a byte specified by the first parameter with 0. If it is 0, it changes it to TRUE and returns OK. If it is not 0, it returns ERROR. LOCK and CMPXCHGB are used to get the atomic memory access.
OK or ERROR if the specified flag is not zero.
pentiumBtc( ) - execute atomic compare-and-exchange instruction to clear a bit
STATUS pentiumBtc (pFlag) char * pFlag; /* flag address */
This routine compares a byte specified by the first parameter with TRUE. If it is TRUE, it changes it to 0 and returns OK. If it is not TRUE, it returns ERROR. LOCK and CMPXCHGB are used to get the atomic memory access.
OK or ERROR if the specified flag is not TRUE