VxWorks BSP Reference : wrSbc8255
wrSbc8255 - Wind River SBC8255
This manual entry provides board-specific information necessary to run VxWorks for the wrSbc8255 BSP. Please read the section "Getting the board running vxWorks" in order to configure the board to run vxWorks.
Getting the board running vxWorks This section will guide you step by step how to get vxWorks running on this board.
1. Setting the board Jumpers & Switches:
In order to get the board running with the default configuration. the
following jumper's and switch's need to be set as follows:.CS
For board with 50Mhz Ocilator:
____________________________________________________________
| Jumpers | Dip Switch S1 | Dip Switch S2 | Dip Switch S6|
|-------------|---------------|---------------|--------------|
|JP1 1-2 | S1-1 Close | S2-1 Close | S6-1 Close|
|JP2 1-2 | S1-2 Close | S2-2 Close | S6-2 Close|
|JP3 Open | S1-3 Close | S2-3 Close | S6-3 Close|
|JP4 Open | S1-4 Close | S2-4 Close | S6-4 Close|
|JP10 1-2 | S1-5 Close | S2-5 Close | S6-5 Close|
|JP16 Open | S1-6 Close | S2-6 Close | S6-6 Close|
|JP25 1-2 | S1-7 Close | S2-7 Close | S6-7 Close|
|JP23 Open | S1-8 Close | S2-8 Open | S6-8 Open |
|_____________|_______________|_______________|______________|For board with 66Mhz Ocilator:
____________________________________________________________
| Jumpers | Dip Switch S1 | Dip Switch S2 | Dip Switch S6|
|-------------|---------------|---------------|--------------|
|JP1 1-2 | S1-1 Close | S2-1 Close | S6-1 Close|
|JP2 1-2 | S1-2 Close | S2-2 Close | S6-2 Close|
|JP3 Open | S1-3 Close | S2-3 Close | S6-3 Close|
|JP4 Open | S1-4 Close | S2-4 Close | S6-4 Close|
|JP10 1-2 | S1-5 Close | S2-5 Close | S6-5 Close|
|JP16 Open | S1-6 Close | S2-6 Open | S6-6 Open |
|JP25 1-2 | S1-7 Close | S2-7 Open | S6-7 Open |
|JP23 Open | S1-8 Close | S2-8 Open | S6-8 Open |
|_____________|_______________|_______________|______________|Other Jumpers setting depend on CS0 connection:
____________________________________________________
|Chipe Select 0 to SIMM FLASH | JP24 1-2 & 3-4|
|---------------------------------|------------------|
|Chipe Select 0 to On Board FLASH | JP24 1-3 & 2-4|
|_________________________________|__________________|.CE
2. Creating a bootrom_uncmp.hex:
2.1 Launch Tornado II, go to the "Build" menu and choose the option
"Build Boot ROM...".
2.2 the "Build Boot ROM" window will popup, in the "Select a BSP:" column
choose the "wrSbc8255", and in the "Select an Image to build:" column
choose "bootrom_uncmp.hex" and press the "OK" button.
2.3 After the build process will finish successfully (You will see "Done" in
the "Build window" without error), you will have the bootrom_uncmp.hex in
your BSP directory "$(WIND_BASE)/target/config/wrSbc8255".3. Programming bootrom_uncmp to SBC8255 FLASH:
If you are using visionCLICK please follow the instruction in section 3.1
if you are using SingleStep please follow the instruction in section 3.23.1 Using visionCLICK:
3.1.1 Install the visionPROBE II or visionICE II and power it on.
Connect the JTAG interface cable from the visionPROBE II or
visionICE II into the SBC8255 board JTAG (JP6 The JTAG Port)
connector.Once all the connections have been made, power up the SBC8255
board and start the visionCLICK executable on the host.3.1.2 Configure the visionCLICK project:
The "Welcome To visionCLICK" window will appear .In this window
press on the "Configure" button, This will invoke "PROJECTS/LOAD"
window. In this window press on the + left to the
"PowerPC_C_Demo.prj".This will show you the project configuration.
Point with the mouse cursor on the "Microprocessors" option and
press the right button and choose the type of CPU you have on your
board. For example: "PowerPC->MPC82xx->MPC8255" . Verify that the
"Target Control" option point to visionPROBE for visionPROBE II or
visionICE for visionICE II, Also switch to the "Communications"
TAB and verify that the "Normal Port/Rate" & "Download Port/Rate"
suite your connection. for example: "LPT1" for visionPROBE II.
Now press the "Save" button at the bottom of the window and after
it on the "Activate" button.3.1.3 Program visionPROBE II / visionICE II with the proper register
setting for the SBC8255 board:Go to the "Tools" menu and select the
"Log Output/Playback Scripts" option. The "Record / Playback"
dialog box will popup. In this dialog box go to the
"Playback Commands From File" group and press on the "Browse"
button. Navigate your self to the location of the following
register file: "sbc8255_64MB.reg" for the board with 64MB SDRAM or
"sbc8255_16MB.reg" for the board with 16MB SDRAM. The file located
in the visionCLICK installation. After choosing the register file
press on the "Open" button to confirm the selected reg file. You
will return back to the "Record / Playback" dialog box. Now press
on the "Start" button located in the same group. In the "Terminal"
window you can see that the visionCLICK is running the script.
When visionCLICK will finish the playback you will get back the
">BKM>" or the ">ERR>".3.1.4 Get into Background Mode:
Execute the "IN" command to reset the board and initialize it with
the register setting..CS
IN
.CSThis command is the reset command to initialize the board.
3.1.5 Setting the Flash Chip Select:
3.1.5.1 Once the ">BKM>" prompt appears we need to verify that the
Flash chip select configure correct. To do this type "CS"
in the "Terminal" window and press Enter. The first line
is for the Flash chip select. This is chip select 0 "CS0"
under the "PS" (From Port Size) column for the first line,
check that the number is 32 For the SIMM Flash or 8 For
the On Board Local Flash. If the number is else follow
the step below in order to change it:3.1.5.2 Type "CS CS0" in the "Terminal" window and press Enter.
.CS
>BKM>CS CS0
.CE3.1.5.3 Press enter until you get the following line:
.CS
(0-3) = 64, 8, 16, 32 bits | Port Size = 32 Bits >
.CEEnter 3 for 32 SIMM Flash or 1 for the On Board Local
Flash and keep pressing Enter until you get again the
">BKM>" prompt.3.1.5.4 Once the prompt appears, reset the board and the emulator
with the following command:.CS
>BKM>IN
.CEAfter you got the ">BKM>" prompt again continue with the
instruction in the next section.3.1.6 Converting the bootrom_uncmp.hex to bootrom_uncmp.bin:
3.1.6.1 In visionCLICK, choose "Convert Object Modules" from the
"Tools" menu. The "CONVERT BINARY AND SYMBOL OBJs" dialog
box will pop up.Select "All Files" in the "Files of Type"
box. Go to the "Select Input Object Module To Convert"
group and navigate to the file "bootrom_uncmp.hex"
located in:
"$(WIND_BASE)/target/config/wrSbc8255/bootrom_uncmp.hex"3.1.6.2 In the group "Binary Downloadable Objects Modules" check
the "Create Flat BIN File For Flash Programming".
"In Range Of 0x" editbox, enter 0 for the start address,
and in the "To 0x" editbox, enter "FFFFFFFF".3.1.6.3 Make sure that all the other check box are unchecked.
Press the "Convert" button. Close the terminal window
when the conversion completes.3.1.7 Programming the SBC8255 Flash:
In visionCLICK, select "Program Flash Devices" from the Tools
pull-down menu. This will invoke the "TF FLASH PROGRAMMING"
window. If you are not using visionCLICK, you can also invoke
this window using the "visionICE Utilities Panel" and follow the
steps below:3.1.7.1 Click the "Select" in the "Flash Card or PC Host File
Name and Path" group. The "CHOOSE A FILE FROM HOST PC"
dialog box will popup. In the edit box enter the full path
to the location of the "bootrom_uncmp.bin", or use the
"<--Browse" button to browse to the file location. Go to
the "+/- Bias" group and enter the number "FFF00100" in
the edit box. Now click the "OK" button, this will bring
you back to the "TF FLASH PROGRAMMING" dialog box.3.1.7.2 In the "Programming Algorithm" group in, the edit box
press on the "Select" button, and select one of the
following Flash devices:The 4MB SIMM FLASH: "AMD 29F080/81(1024 x 8) 4 Devices"
The 2MB On Board FLASH: "AMD 29F016/17(2048 x 8) 1 Device"
** Note: In order to use the On Board FLASH some jumpers
and switches should be changed.3.1.7.3 Set the proper address of the Flash to "FFF00000", check
the "Erase All" radio button,and set the
"Available RAM Workspace" setting to "00000000", set the
"Bytes Of Target RAM Required" to "60000".3.1.7.4 Press the "Erase and Program" button.
3.1.7.5 Now the Flash memory is programmed with the new boot
program.3.2 Using SingleStep for vision:
3.2.1 Install the visionPROBE II or visionICE II and power it on.
Connect the JTAG interface cable from the visionPROBE II or
visionICE II into the SBC8255 board JTAG (JP6 The JTAG Port)
connector.Once all the connections have been made, power up the SBC8255
board and start the SingleStep for vision executable on the host.3.2.2 Configure the SingleStep project:
3.2.2.1 Go to the "File" menu and choose the
"Start Debug Session..." .3.2.2.2 The "Debug" dialog box will popup, In the "Connection" tab
choose the visionPROBE option & the correct LPT port if
you are using visionPROBE, or visionICE & enter the
emulator IP address if you are using visionICE.3.2.2.3 In the "Processor" tab choose the "MPC8255".
3.2.2.4 In the "Register" tab choose the option
"Use vision-style register window with REG file" and then
browse to the location of the file "sbc8255_64MB.reg" for
board with 64MB SDRAM or "sbc8255_16MB.reg" for board with
16MB SDRAM, and choose it. The "sbc8255_64MB.reg" or
"sbc8255_16MB.reg" file should be in the SingleStep
registers directory.3.2.2.5 In the "File" tab choose the "Debug without a file"
option.3.2.3 Get into Background Mode:
3.2.3.1 Now in the "File" tab press OK.
3.2.3.2 Now should get the "Debug Status" dialogbox and in the
"Debug Session" field you should have in green
"Started Successfully", press the "Close" button.3.2.3.3 Now go to the "Command" button in the toolbar and press on
it. The "Command" Window will popup, the prompt in the
window will be "SingleStep". Bring the mouse cursor above
the "Command" window and press the right button. A menu
will popup, choose the "VisionShell(vsh)" option. Now the
prompt in the window will be ">BKM>". If the prompt is
">ERR>" execute the "IN" command to reset the board and
initialize it with the register setting..CS
IN
.CS
This command is the reset command to initialize the board.
After you got the ">BKM>" prompt again continue with the
instruction in the next section.3.2.4 Setting the Flash Chip Select:
3.2.4.1 Once the ">BKM>" prompt appears we need to verify that the
Flash chip select configure correct. To do this type "CS"
in the "Command" window and press Enter. The first line
is for the Flash chip select. This is chip select 0 "CS0"
under the "PS" (From Port Size) column for the first line,
check that the number is 32 For the SIMM Flash or 8 For
the On Board Local Flash. If the number is else follow
the step below in order to change it:3.2.4.2 Type "CS CS0" in the "Command" window and press Enter.
.CS
>BKM>CS CS0
.CE3.2.4.3 Press enter until you get the following line:
.CS
(0-3) = 64, 8, 16, 32 bits | Port Size = 32 Bits >
.CEEnter 3 for 32 SIMM Flash or 1 for the On Board Local
Flash and keep pressing Enter until you get again the
">BKM>" prompt.3.2.4.4 Once the prompt appears, reset the board and the emulator
with the following command:.CS
>BKM>IN
.CEAfter you got the ">BKM>" prompt again continue with the
instruction in the next section.3.2.5 Converting the bootrom_uncmp.hex to bootrom_uncmp.bin:
3.2.5.1 Go to the menu and choose "Tools" and
"Vision Flash Utility..." .3.2.5.2 The "Flash Programming Window" will popup. Go to the
"Files" tab, press the "Convert" button.3.2.5.3 The "File Convertion" window will popup. In the
"Enter new start address" edit box type "0x0" and in the
"Enter new end address" edit box type "0xFFFFFFFF".3.2.5.4 Now press the "Convert" button. After the convert operation
finished, you will see it in the "Convert Result" section
press the "Close" button.3.2.6 Programming the SBC8255 Flash:
3.2.6.2 In the "Flash Programming Window" window. Go to the
"Configuration" tab, & choose the following Flash device:The 4MB SIMM FLASH: "AMD 29F080/81(1024 x 8) 4 Devices"
The 2MB On Board FLASH: "AMD 29F016/17(2048 x 8) 1 Device"
** Note: In order to use the On Board FLASH some jumpers
and switches should be changed.In "Flash Bank" group for the "Start:" enter "FFF00000".
In the "RAM Workspace" group for the "Workspace Start at:"
enter "00000000" and for the "Workspace Size:" enter
"60000".3.2.6.3 Now switch to the "Files" tab and press the "Add" button.
The open dialogbox will popup, browse to
"$(WIND_BASE)\target\config\wrSbc8255 "bootrom_uncmp.bin" file. Now after getting back to the
"Files" tab you will see the full path to the selected
file in the "Binary Files" group. Move the mouse curser
above the line that showing the full path in the
"Binary Files" group and press the right button to mark
this line. Now press the "Toggle Enable" button to select
this binary file. Make sure that the line is still marked,
and press the "Edit" button on the right. The "File Edit"
dialog box will popup. In the "Enter new start address"
edit box enter "0xFFF00100" and press the "OK" button.3.2.6.4 Now go to the "Program" tab and press the "Erase/Program"
button.3.2.6.5 Now the Flash memory is programmed with the new boot program.
4. Running the VxWorks Boot ROM program:
4.1 Disconect visionPROBE II or the visonICE II if it still connected to the
board, because it still connected to the board in some case it can stop
the processor at the first instruction.4.2 Connecting the Ethernet channel and the serial channel:
4.2.1 First, connect the supplied serial cable with the board. On
one said connect the RJ11 connector to the COM1 (JP13) port on the
the SBC8255, and on the other said use the RJ11 to 9/25 Pin
addapter to connect it to your host. The UART devices is set as
follow: 8 data bits, 1 stop bit, hardware handshaking, and parity
disabled. The serial console (9600 bps).4.2.2 Second, plug the Fast Ethernet transceiver that came with the
board to the MII conector on the board (JP15). Connect a
standard Ethernet cable to the the RJ45 connector on the Fast
Ethernet transceiver.4.3 Launch a terminal program on the host said, and configures it according
to the following details: 8 data bits, 1 stop bit, hardware handshaking,
and parity disabled. The serial console (9600 bps).4.4 Now to execute this new boot program turn the board off,and on. and you
should get the vxWorks boot count down on the terminal window. Press any
key to stop the count down. Now follow the instruction in the
instructions in the "Getting Started" chapter of the
"VxWorks Programmer's Guide." for more detail how to configure vxWorks.
bootrom_uncmp.hex is provided with this BSP. The bootrom_uncmp is configured to a ROM base address of 0x0 and includes, also it's configured to use the 2 MByte On Board FLASH and FCC2 10/100BaseT Ethernet as default boot device and SMC1 as console device. The hard reset configuration word must be programmed separately at the flash base address of 0xFE000000 and at offsets 0x0, 0x8, 0x10 and 0x18, see chapter 5 Reset in the MPC8260 PowerQUICC II User's Manual.
The following section will explain how to launch VxWorks using visionWARE as a boot loader. Please follow the steps below:Note: Before using vsionWARE you need to verify that visionWARE is programmed
to you FLASH. If visionWARE is not exist on your FLASH, please see
"Programming bootrom_uncmp to SBC8255 FLASH" section how to program the
SBC8260 Flash, also you can skeep step 3.1.6 or 3.2.5 that explain how to
convert the bootrom_uncmp.hex to *.bin, and instead of programming the
"bootrom_uncmp.bin" program the "vWARE.bin" file.1. Connect your SBC8255 serial channel (COM1) to a host running terminal
program at 9600 baud rate (For example HyperTerminal) using the
supplied serial cable.2. Connect your SBC8255 100Base-T (JP15) port using the Fast Ethernet
Transceiver to a network hub.3. Open TFTP server and point to the location of the vxWorks.bdx file. If
you want to use the TFTP server that is supplied with visionWARE, go to
the visionWARE directory on your host, insaide the visionWARE root
directory you will find "tftp" directory that contain application called
"tftpd32.exe" . Run this application and the TFTPD32 window will popup.
In the TFTPD32 window press on the "Settings" button. This will invoke
the "Tftpd32: Settings". Go to the "Base Directory" group and inside the
edit box type the full path to your vxWorks image, or use the "Browse"
button to navigate to there.4. Power up your SBC8255 and press any key within 3 seconds from the serial
terminal to abort the boot script. This will display a ">BKM>" prompt.5. Type the "shell" command and press enter. Now you should get the
following line: "Command Channel = 0: serial >" Press enter.6. Next line will be: "Boot Delay (seconds) = 1 >". Here you need to
specify the disaierd delay value and press enter.7. Nex line will be: "Boot Script = >". Here you need to give the boot
script command. Please type the following:
"load \host\vxWorks.bdx!launch 100000" . Where "host" is the host
name, and press enter.Note(s):
** It is very important to keep the same space between the "load"
command and the host name "\host".** It is very important to keep the same space between the "launch"
command and the "100000".** The host name should be the same as specified in the
"Remote System 1 Name" line.8. Next line will be "Prompt String = BKM >" . Press enter.
9. Next line will be "MAC Address = 00-00-00-00-00-00 >" . If you want to
change the target MAC address, type it now and press enter, else press
just enter.10. Next line will be "IP Address = 0.0.0.0 >". Type your target IP address.
For example: 192.168.199.0 and press enter.11. Next line will be "Subnet Mask = 0.0.0.0 >" . If you want to use subnet
mask, type it now and press enter,
else just press enter.12. Next line will be "Default Gateway = 0.0.0.0 >" . If you want to use
default gateway, type it now and press enter, else just press enter.13. Next line will be "Remote System 1 Name = >" . Here you need to type
the same host name you specified in the "Boot Script" line.14. Next line will be "Remote System 1 IP = >" . Here you need to type
your host IP address. For example: 192.168.199.1 and press enter.15. Next line will be "Remote System 2 Name = >" . Just press enter.
16. Next line will be "Remote System 3 Name = >" . Just press enter.
17. Next line will be "Remote System 4 Name = >" . Just press enter.
18. Now you will get the following message:
Saving changes will generate a reboot.
Save Changes (y/n)?Press y to save the changes.
19. Now the changes are saved and the board will restart visionWARE and
boot vxWorks, after a few seconds you will get the following messages:Wind River visionWARE v2.00 for the SBC8260 Board MAC : 00-00-00-00-00-00 IP : 192.168.199.0 Type "shell" to set IP and/or MAC addresses Type "help" to see available commands Press a key in the next <1> seconds to preempt boot script Booting from script... load \\host\vxWorks.bdx!launch 100000 >Attached TCP/IP interface to motfcc unit 0 Attaching interface lo0...done VxWorks Copyright 1984-1998 Wind River Systems, Inc. CPU: MPC8255 PowerQUICC II -- Wind River. SBC8255 VxWorks: 5.5 BSP version: 1.2/12 Creation date: Sep 23 2001 WDB: Ready.For more information regarding visionWARE boot services and the visionWARE development kit, please refer to the visionWARE manuals, located on the CD that was shipped with your board.
The supported boot device(s) is(are):
motfcc - MII 10/100BaseT Fast Ethernet (FCC2)
motscc - 10BaseT Ethernet (SCC1)
This section describes the support and unsupported features of the SBC8255
The supported features of the SBC8255 board are:
8255 processors
Board Initialization
MMU support
Cache support
Decrementer timer, is used to implement a System Clock.
SMC1 a UART for COM1 (Consol channel).
SMC2 a UART for COM2.
SCC1 Port as an Ethernet device supporting 10Base-T protocol.
FCC2 Port as an Ethernet device supporting 10/100Base-T protocol.
TIMER2 as an 16-bit auxiliary clock.
TIMER3 and TIMER4 are cascaded into a free-running 32-bit timer for
timestamp support.
8255 SIU Interrupt Controller.
Baud Rate Generators as required for SMC1 and SMC2.
64MB/16MB SDRAM on 60x bus.
4MB SIMM FLASH on 60x bus.
2MB On Board FLASH on 60x bus.
4MB SDRAM on Local bus.
32KByte EEPROM for Ethernet MAC address and bootline.
150/200 MHZ Core speeds
100/133 MHZ CPM speeds
50/66 MHZ Oscilator
The items not supported on the SBC8255 are:
virtual DMA
Parallel Ports
Baud Rate Generators not used by supported devices
SPI
I2C
SCC2, SCC3 and SCC4
ATM, Transparent, or HDLC protocols on FCC1
FCC3
MCC1 and MCC2
Any of the eight TDM interfaces
Support for the PCI bridge
Support for the L2 cache (hardware not available)
This section documents the details of the device drivers and board hardware elements for the SBC8255.
L1 cache locking is available for MPC8255. The cache lock routine can be used to lock the entire data or instruction cache with a specified memory region.
The SBC8255 is equipped with four parallel I/O ports, each comprised of 32 discrete I/O pins. sysIOPort.c is a sample code for reading / writing I/O pin states and connecting an interrupt handler that triggers on a pin state transition.TrueFFS support
This BSP supports the optional product TrueFFS for Tornado. To use TrueFFS install the product, define the following macro in "config.h":
#undef INCLUDE_TFFS
#define INCLUDE_TFFSTrueFFS is set up to use the second Flash (Not the boot FLASH). That means the FLASH that connected to CS6. If the boot FLASH is the 2MB On Board FLASH then the TFFS is set up to use the 4MB SIMM FLASH. If the boot FLASH is the 4MB SIMM FLASH then the TFFS is set up to use the 2MB On Board FLASH.
The chip drivers included are:
smc8260Sio.c - serial driver m8260IntrCtl.c - interrupt controller driver m8260Timer.c - timer driver byteNvRam.c - Byte oriented nvram device eeprom.c - EEPROM access routines m82xxDpramLib.c - DPRAM memory driver. m8260SccEnd.obj - SCC Ethernet END driver motFccEnd.o - FCC Ethernet END driver miiLib.o - Media Independent Interface libraryThe BSP configures SMC1 as a UART to implement a console device and the FCC2 as an Ethernet. SMC1 is used as a console device. SCC1 is used as a 10Base-T Ethernet port. FCC2 is used as a 10/100Base-T Ethernet port.
Memory Map from CPU point of view
Chip Select Start Size Access to
------------------------------------------------------------------
CS2-3 (R/W) 0x0 16MB (min) DIMM SDRAM
CS5 (R/W) 0x22000000 32KB (min) NVRAM (EEPROM)
0x0F000000 64KB SBC8255 internal DPRAM
CS0-1 (R/W) 0xFFC00000 4MB (min) SIMM FLASH memory
CS6 (R/W) 0xFFE00000 2MB On Board Local FLASH
CS4 (R/W) Local Bus 4MB SDRAM on Local bus
CS7 (W) 0x21000001 8Bit User LED's (Register)
CS7 (R) 0x21000001 8Bit User Switch's (Register)
CS7 (R) 0x21000000 8Bit Present Detect (Register)
1. Power off the SBC8255 board and set dip switch S2-1 to Open position
(Sets Reset Configuration to internal default).2. Verify JP-24 jumper is set to 1-3 and 2-4 if you boot from the Local Flash.
3. Power on the SBC8255 and the emulator (visionPROBE II or visionICE II).
4. If you are using visionCLICK follow section 4.1, if you are using SingleStep
for vision follow section 4.2 :4.1 Using visionCLICK:
4.1.1 In the terminal window at the ">BKM>" or ">ERR>" prompt enter the
"IN" command and press enter. Now you should get the ">BKM>"
prompt.4.1.2 Continue to step 5.
4.2 Using SingleStep for vision:
4.2.1 Go to the "File" menu and choose the "Start Debug Session..." .
4.2.2 The "Debug" dialog box will popup, In the "Connection" tab
choose the visionPROBE option & the correct LPT port if you
are using visionPROBE, or visionICE & enter the emulator IP
address if you are using visionICE.4.2.3 In the "Processor" tab choose the MPC8255.
4.2.4 In the "File" tab choose the "Debug without a file" option
and press OK.4.2.5 Now should get the "Debug Status" dialogbox and in the
"Debug Session" field you should have in green
"Started Successfully", press the Close button.4.2.6 Now go to the "Command" button in the toolbar and press on it. The
"Command" Window will popup, the prompt in the window will be
"SingleStep". Bring the mouse cursor above the "Command" window
and press the right button. A menu will popup, choose the
"VisionShell(vsh)" option. Now the prompt in the window will be
">BKM>".4.2.8 Cotinue to step 5.
5. At the ">BKM>" prompt enter:
If you are using the 2MB On Board FLASH: AMD 29F016B (2048 x 8) 1 Device,
(8 Bit).
50Mhz Oscilator 66Mhz Oscilator --------------- --------------- SY RSTCONF 04320206 8 SY RSTCONF 04320205 8
If you are using the 4MB SIMM FLASH: AMD 29F080B (1024 x 8) 4 Device,
(32 Bit).
50Mhz Oscilator 66MHZ Oscilator --------------- --------------- SY RSTCONF 0C320206 32 SY RSTCONF 0C320205 32
The emulator should respond with the following:
+ Flash Erase : Success + Program Configuration Word : Success >BKM>6. Power off the SBC8255 and close switch S2-1. You will get the ">ERR>"
prompt in visionCLICK "Terminal" window or in SingleStep "Command" window.7. Power on the SBC8255 and at the ">ERR>" prompt enter: "IN"
8. The SBC8255 will read the configuration word from Flash during reset and
initialize the processor base on the configuration word entered in step 5
and you will get to ">BKM>".9. Now you are ready to disconnect the emulator and run the BSP.
In order to use the 66Mhz Oscilator instead of the 50Mhz you need to follow those steps:
1. Power off the SBC8255 board and set dip switch S2-1 to Open posetion
(Sets Reset Configuration to internal default).2. Change the following switches:
___________________________________
| 66Mhz Oscilator | 50Mhz Oscilator |
|-----------------|-----------------|
| S2-6 Open | S2-6 Close |
| S2-7 Open | S2-7 Close |
| S2-8 Open | S2-8 Open |
|_________________|_________________|The BSP have the option to determine the CPU's Core Speed, the speed
at which to run the CPM, and the Input Xtal Speed Automatically by
reading the user switch. The BSP can also be configured to determine
this information Manually.2.1 In order to determine the speed manually follow those steps:
2.1.2 In "config.h" define the MPC8255PART parameters as follow:
For 50Mhz Oscilator:
.CS
#define MPC8255PART MPC8255_150_100_50_PART
.CEFor 66Mhz Oscilator:
.CS
#define MPC8255PART MPC8255_200_133_66_PART
.CENote(S): 8260 devices are marked: XPC[MPC]8255xxx core
speed/cpm speed/clock speed. In this example, the
chip was marked as 200/133/66Mhz. The board had a
66Mhz Oscillator as a clock. Also in this case, the
core is run at 200.Each time "config.h" is edited, new vxWorks and
bootrom images should be built and Flash memory is
to be programmed.3. Now please go to the section above:
"Programming the Hard Reset Configuration Word to the On Board/SIMM FLASH"
and follow the instructions on how to program the new Hardware Reset
Configuration Word that will match your setting.
Initial boards and bsps were supplied with a 16Meg SDRAM SIMM; more recent evaluation boards are supplied with a 64Meg SIMM. the BSP is logically setup for 64Meg of SDRAM. The 64Meg is divided into two halves. The first 32Meg is useable for code and data. The second 32Meg is specified as USER_RESERVED_MEM memory. The 64Meg option is specified as a #define in the "config.h" file. If your board comes with 16Meg of SDRAM change the following macro in "config.h". From:
#undef INCLUDE_16MEG_SDRAM #define INCLUDE_64MEG_SDRAM /* (requires hardware modification) */To:#define INCLUDE_16MEG_SDRAM #undef INCLUDE_64MEG_SDRAM /* (requires hardware modification) */The reason the BSP divides the 64Meg SDRAM into two 32Meg sections has to do with the EABI compilation option of a 24 bit address. The default compilation options generates a "bl" for branch instructions. This increases performance, but places a 32Meg address limit on the code.There are two "work arounds" to this limitation.
1.) recompile all the source with the -mlongcall compilation flag
2.) add remaining 32Meg to the memory pool vi the memAddToPool( ) function.Option #1 would require all the libraries, driver, and the BSP to be recompiled with the -mlongcall compiler option. This results in a number of code changes; the most obvious code change is branches are implemented via brlr instruction verses the bl instruction.
Option #2, the perferrable options, requires the USER_RESERVED_MEM and the memAddToPool( ) constructs be used to specify the remaining 32Meg to be added to the memory pool. Consult WindTech Note WTN41 for details on specifying user memory.
** Note: Don't forget to change the "RAM_HIGH_ADRS" value in the makefile to be
the same as in "config.h". For 16Meg "00E00000" and for 64Meg
"01E00000".
The BSP configures to use FCC2 as an Ethernet port. The name "motfcc" should be specified as the boot device to the boot ROMs when booting vxWorks over that interface. The Fast Ethernet Controller (FCC) makes available fast Ethernet connectivity through the use of a 10/100BaseT Ethernet transceiver conected to the MII port (JP21) and a RJ45 connector. The BSP configures to use END-style network driver. If you wishes to use the SCC1 as the boot device you need disable FCC2, and use SCC1 instead. Do this by changing in "config.h" the macro from "#define BOOT_DEVICE FCC_END" to "#define BOOT_DEVICE SCC_END", also the name "motscc" should be specified as the boot device to the boot ROMs when booting vxWorks over that interface. Each time config.h is edited, new vxWorks and bootrom images should be built and Flash memory is to be programmed.
This BSP implements NvRam via a EEPROM device. There are a few user parameters associated with this device. The parameters are located in the "config.h" file and are:#undef INCLUDE_EEPROM_LOCKING #define SMART_EEPROM_WRITE #define ETHERNET_ADR_SET /* (used in bootConfig.c to enable 'N' command) */The INCLUDE_EEPROM_LOCKING parameter is typically #undef'ed. If #define'ed, the EEPROM will be software locked between accesses. This was implemented on the BSP to work around a power-on EEPROM corruption problem. It should be noted, that if the EEPROM is locked, its contents can not be altered via an emulator or visionPROBE II or visionICE II (JTAG does not meet the minimum timing relationships needed).The SMART_EEPROM_WRITE parameter is typically #define'd. When defined, the EEPROM write code first checks to see if a cell is the desired value. If the memory location already contains the desired value, the write is skipped. This was implemented to increase the life of the EEPROM device.
The ETHERNET_ADR_SET is a value that indicates the MAC address is stored in NVRAM and alterable via the N bootrom command.
The SBC8255 boards do not have a unique Ethernet hardware address assigned to each board. A unique address is absolutely necessary if the user wishes to connect the board to a network. Thus, the user must provide a suitable 6 byte Ethernet address for each board used on a network. The default Ethernet Address is specified in the "config.h" The following relate to the storage of the Ethernet address in NVRAM:
/* Ethernet MAC Address Parameters */ #define CUST_ENET3 0x01 /* Customer specific portion of MAC address */ #define CUST_ENET4 0x02 #define CUST_ENET5 0x03The first three bytes (0x00, 0xa0, 0x1e) are a Wind River specific prefix that should be kept as-is. If for some reason you need to change them, in "config.h" change the following macros:
#define WR_ENET0 0x00 /* Wind River specific portion of MAC (MSB->LSB) */ #define WR_ENET1 0xa0 #define WR_ENET2 0x1e #define ENET_DEFAULT 0x1ea00000 NOTE: The bytes are reversed in the #define due to little endian issues in the macro that processes the ENET_DEFAULT macro.Note:
The "ENET_DEFAULT" macro should contain the same number as the three
"WR_ENETx" macros. For example :
#define WR_ENET0 0x11 #define WR_ENET1 0x22 #define WR_ENET2 0x33 #define ENET_DEFAULT 0x33221100The user must change the last three bytes from 0x03, 0x02, 0x01 to three unique bytes (i.e., bytes not used by any other Wind River Ethernet connection on your net). Check with your system administrator if you do not know this information. If these bytes need changing (they often will not), a new boot ROM must be burned, and a new image must be built. Ethernet Address can be specified at the bootrom prompt (N command). The Ethernet address is stored in the on board NVRAM. This option will able you to change the last three bytes. To use this option, open the console window (for example: hayper terminal) and when the bootrom banner appear and the countdown start, press any key, when you get the [VxWorks Boot] prompt , press N and follow the instructions.
The BSP configures to use the 2MByte Local Flash. In order to use the 4MByte SIMM Flash instead , change in "config.h" the following lines:
#define BOOT_FLASH ON_BOARD_FLASH
#define BOOT_FLASH SIMM_FLASHNew boot ROM must be burned, and a new image must be built.**Note: You need also to change the jumpers and switch's configuration. For
more details see "Setting the board Jumpers & Switches" section in
this file.
SMC1 and SMC2 are configured as UART devices with 8 data bits, 1 stop bit, hardware handshaking, and parity disabled.
This VxWorks MPC8255 BSP uses a simple 3 wire connection and standard RJ11 where pin 1 = RIN, pin 2 = TOUT, pin 3 = NC, and pin 4 = GND.
There is no SCSI interface on this board.
SCC1 is configured as a 10Mb/s Ethernet port FCC2 is configured as a 10/100Mb/s Fast Ethernet port
There is PCI interface on this board, but the current version of the CPU is not supporting PCI interface, also the BSP dosn't support PCI.
If the FORCE_DEFAULT_BOOT_LINE is defined (in config.h), then the DEFAULT_BOOT_LINE parameters are used as boot parameters regardless of the NVRAM values previously specified. Recall, boot parameters are stored in the NVRAM device so boot parameters are not lost during a power cycle.Defining the FORCE_DEFAULT_BOOT_LINE value is useful for debugging visionICE II/visionPROBE II downloaded RAM based vxWorks images. It is considered a DEBUG options so it should be #undef'ed for the final image.
Normally the boot parameters are specified at the bootrom prompt and stored in NVRAM.When a downloaded image executes, the boot parameters are retrieved from the NVRAM device.
This can sometimes cause undesired results. For example, if the NVRAM has been previously initialized, then changing the DEFAULT_BOOT_LINE in the "config.h" will not result in the new settings being used. The reason being is the initialization code always takes the boot parameters from the NVRAM device. If there are sane values in the NVRAM device, these boot parameters are used.
If you intended to debug an image by downloading with WR's visionTools and plan on changing the DEFAULT_BOOT_LINE parameters a number of times, it might be convenience to define this FORCE_DEFAULT_BOOT_LINE parameter.
As a note, unitialized NVRAM device is initialized automatically with the DEFAULT_BOOT_LINE parameters specified in the "config.h" file.
As an alternate solution for the above scenario, the boot parameters can be changed via the bootrom. This will store the values in NVRAM and will subsequentially be used by the download image. This would require a sane bootrom and would require the target board to run via the bootroms to set the values and then halted to download the image to be debugged via the WR Tools.
If a you configures SCC or FCC use of local bus, or is building a ROM resident image, then you MUST define INCLUDE_LOCAL_BUS_SDRAM in "config.h" as follow:
#undef INCLUDE_LOCAL_BUS_SDRAM
#define INCLUDE_LOCAL_BUS_SDRAM
Before you build a rom resident vxWorks image you need to modify the following parameter in "config.h" :
#undef FORCE_DEFAULT_BOOT_LINE
#define FORCE_DEFAULT_BOOT_LINEDon't forget to enter the correct target IP address in the DEFAULT_BOOT_LINE. For more details please read the "Force Default Boot Line Option" section.And in "config.h" to define the macro "#define INCLUDE_LOCAL_BUS_SDRAM".
** With the ROM RESIDENT from the user level, Zero Copy sockets is available,
but the driver will internally and transparently convert the transmit calls
to copy sends.
The BSP is using by default the FCC channel for booting, but it also include the SCC interface, and you can choose between them in the boot prompt. There is also an option to include the only one of the interfaces. Please follow those steps to get the BSP working only with the SCC or FCC driver instead of working with both of them:1. In "config.h" change the following lines:
FROM:
#define BOOT_DEVICE SCC_FCC_END
TO for Only the SCC Channel:#define BOOT_DEVICE SCC_ENDOR TO for Only the FCC Channels:#define BOOT_DEVICE FCC_END2. In the makefile change the following lines:FROM:
MACH_EXTRA = m8260SccEnd.objTO for Only the FCC Channels:MACH_EXTRA = #m8260SccEnd.obj3. Now rebuild the bootrom and create a new VxWorks image project and build it.** Don't forget to change the device name to "motscc" in the "boot device" line
in the bootrom if you want to use the SCC channel.
bootrom_uncmp.hex is provided with this BSP. The bootrom is configured to a ROM base address of 0x0. When programing the bootrom to the FLASH an offset of 0xFFF00100 need to be given, also it's configured to use the 2 MByte On Board Flash ROM and FCC2 10/100BaseT Ethernet as default boot device and SMC1 as console device. The hard reset configuration word must be programmed separately at the flash base address of 0xFE000000 and at offsets 0x0, 0x8, 0x10, 0x18 and 0x20, see chapter 5 Reset in the MPC8260 PowerQUICC II User's Manual.
The following images are delivered with the wrSbc8255 BSP:
bootrom_uncmp bootrom_uncmp.hex bootrom bootrom.hex vxWorks vxWorks.st m8260SccEnd.obj
Only bootrom_uncmp, bootrom, bootrom_res, vxWorks, vxWorks_romResident have been tested.
The wrSbc8255 is using the m82xxDpramLib.c to allocate dynamically the necessary DPRAM memory for the serial and Ethernet channels. Key features of sysDpramLib are:- Init the DPRAM memory with considerations of any Microcode that add been
loaded.- Allocate aligned and non aligned memory.
- Free memory.
- Manage a special section (b000 - c000) for special FCC needs.
- Manage a special section (8000 - 9000) for special SCC needs.
The following table describes the relationship between the interrupt number, interrupt vector, and the interrupt bit position in the SIU Interrupt Mask Register (SIMR_H and SIMR_L). Also described is the mask to use to enable all interrupts of a higher priority.
.bp
Default Mask to Enable Interrupt Interrupt Interrupt SIMR Higher Priority Interrupts Interrupt Priority Number Vector Mask SIMR_H SIMR_L Source _ HIGHEST PRIORITY 1 16 0x10 H 0x00000004 0000_0000 0000_0000 TMCNT 2 16 0x10 H 0x00000004 0000_0000 0000_0000 TMCNT 3 17 0x11 H 0x00000002 0000_0004 0000_0000 PIT 4 reserved 5 19 0x13 H 0x00004000 0000_0006 0000_0000 IRQ1 6 27 0x20 L 0x80000000 0000_4006 0000_0000 FCC1 7 28 0x21 L 0x40000000 0000_4006 8000_0000 FCC2 8 29 0x22 L 0x20000000 0000_4006 C000_0000 FCC3 9 inactive 10 unused 11 31 0x24 L 0x08000000 0000_4006 E000_0000 MCC1 12 32 0x25 L 0x04000000 0000_4006 E800_0000 MCC2 13 inactive 14 inactive 15 20 0x13 H 0x00002000 0000_4006 EC00_0000 IRQ2 16 21 0x14 H 0x00001000 0000_6006 EC00_0000 IRQ3 17 22 0x15 H 0x00000800 0000_7006 EC00_0000 IRQ4 18 23 0x16 H 0x00000400 0000_7806 EC00_0000 IRQ5 19 unused 20 35 0x28 L 0x00800000 0000_7C06 EC00_0000 SCC1 21 36 0x29 L 0x00400000 0000_7C06 EC80_0000 SCC2 22 37 0x2A L 0x00200000 0000_7C06 ECC0_0000 SCC3 23 38 0x2B L 0x00100000 0000_7C06 ECE0_0000 SCC4 24 inactive 25 inactive 26 inactive 27 inactive 28 unused 29 40 0x30 H 0x00010000 0000_7C06 ECF0_0000 PC15 30 12 0x0C L 0x00000010 0001_7C06 ECF0_0000 Timer 1 31 41 0x31 H 0x00020000 0001_7C06 ECF0_0010 PC14 32 unused 33 42 0x32 H 0x00040000 0003_7C06 ECF0_0010 PC13 34 10 0x0A L 0x00000040 0007_7C06 ECF0_0010 SDMA Bus Error 35 6 0x06 L 0x00000400 0007_7C06 ECF0_0050 IDMA1 36 unused 37 43 0x33 H 0x00080000 0007_7C06 ECF0_0450 PC12 38 44 0x34 H 0x00100000 000F_7C06 ECF0_0450 PC11 39 7 0x07 L 0x00000200 001F_7C06 ECF0_0450 IDMA2 40 13 0x0D L 0x00000008 001F_7C06 ECF0_0650 Timer 2 Interrupts, continued:
Default Mask to Enable Interrupt Interrupt Interrupt SIMR Higher Priority Interrupts Interrupt Priority Number Vector Mask SIMR_H SIMR_L Source _ HIGHEST PRIORITY 41 45 0x35 H 0x00200000 001F_7C06 ECF0_0658 PC10 42 unused 43 unused 44 3 0x03 L 0x00002000 003F_7C06 ECF0_0658 RISC Timer Table 45 1 0x01 L 0x00008000 003F_7C06 ECF0_2658 I2C 46 unused 47 46 0x36 H 0x00400000 003F_7C06 ECF0_A658 PC9 48 47 0x37 H 0x00800000 007F_7C06 ECF0_A658 PC8 49 24 0x18 H 0x00000200 00FF_7C06 ECF0_A658 IRQ6 50 8 0x08 L 0x00000100 00FF_7E06 ECF0_A658 IDMA3 51 25 0x19 H 0x00000100 00FF_7E06 ECF0_A758 IRQ7 52 14 0x0E L 0x00000004 00FF_7F06 ECF0_A758 Timer 3 53 unused 54 unused 55 48 0x38 H 0x01000000 00FF_7F06 ECF0_A75C PC7 56 49 0x39 H 0x02000000 01FF_7F06 ECF0_A75C PC6 57 50 0x3A H 0x04000000 03FF_7F06 ECF0_A75C PC5 58 15 0x0F L 0x00000002 07FF_7F06 ECF0_A75C Timer 4 59 unused 60 51 0x3B H 0x08000000 07FF_7F06 ECF0_A75E PC4 61 unused 62 9 0x09 L 0x00000080 0FFF_7F06 ECF0_A75E IDMA4 63 2 0x02 L 0x00004000 0FFF_7F06 ECF0_A7DE SPI 64 52 0x3C H 0x10000000 0FFF_7F06 ECF0_E7DE PC3 65 53 0x3D H 0x20000000 1FFF_7F06 ECF0_E7DE PC2 66 4 0x04 L 0x00001000 3FFF_7F06 ECF0_E7DE SMC1 67 unused 68 5 0x05 L 0x00000800 3FFF_7F06 ECF0_F7DE SMC2 69 54 0x3E H 0x40000000 3FFF_7F06 ECF0_FFDE PC1 70 55 0x3F H 0x80000000 7FFF_7F06 ECF0_FFDE PC0 71 unused 72 unused 73 reserved LOWEST PRIORITY
This section describes miscellaneous information that the user needs to know about the BSP.
The MPC8255 is not maintaining cache coherency between the 603 core and the CPM, in result of this, all the data that is transfer from the 603 to the CPM an vise versa should be placed in non-cacheable memory. For example the FCC and SCC buffers and buffer descriptors should be allocated using cacheDmaMalloc( ). In this BSP the BD are located inside the CPM DPRAM, that means only the buffers are on the 60x bus, and they are non-cacheable.
If both the MOT_SCC_END and MOT_FCC_END driver are installed, the CPM Driver must be installed in endDevTbl[] first. This is a bug and probably has something to do with port pin set up order.
MAC Address not being displayed properly from ifShow( ).
Embedded Support Tools SBC8260 Hardware Reference Manual MPC8260 PowerQUICC II User's Manual MPC8260UM/D PowerPC Microprocessor Family: The Programming Environments for 32-bit Microprocessors MPCFPE32B/AD MPC603e & EC603e RISC Microprocessors User's Manual MPC603EUM/AD