VxWorks BSP Reference : wrSbc405gp
wrSbc405gp - Wind River SBC405GP
This manual entry provides board-specific information necessary to run VxWorks for the wrSbc405gp BSP. Please read the section "Getting the board running vxWorks" in order to configure the board to run vxWorks.
Getting the board running vxWorks This section will guide you step by step how to get vxWorks running on this board.
1. Setting the board Jumpers & Switches:
In order to get the board running with the default configuration. the
following jumper's and switch's need to be set as follows:.CS
___________________________________________________
| CPU Configuration Switch Box |
|___________________________________________________|
| Dip Switch SW6 | Dip Switch SW5 | Dips Switch SW4 |
|----------------|----------------|-----------------|
| SW6-1 On | SW5-1 On | SW4-1 On |
| SW6-2 On | SW5-2 Off | SW4-2 Off |
| SW6-3 On | SW5-3 Off | SW4-3 On |
| SW6-4 Off | SW5-4 Off | SW4-4 Off |
| SW6-5 Off | SW5-5 On | SW4-5 Off |
| SW6-6 Off | SW5-6 Off | SW4-6 On |
| SW6-7 Off | SW5-7 On | SW4-7 Off |
| SW6-8 Off | SW5-8 Off | SW4-8 On |
|________________|________________|_________________|__________________ _______________________
| User Switch Bank | | EPLD Isolation Switch |
|__________________| |_______________________|
| Dip Switch SW3 | | Dip Switch SW1 |
|------------------| |-----------------------|
| SW3-1 Off | | SW1-1 On |
| SW3-2 Off | | SW1-2 On |
| SW3-3 Off | | SW1-3 On |
| SW3-4 Off | | SW1-4 On |
| SW3-5 Off | |_______________________|
| SW3-6 Off |
| SW3-7 Off |
| SW3-8 Off |
|__________________|.CE
2. Creating a bootrom_uncmp.hex:
2.1 Launch Tornado II, go to the "Build" menu and choose the option
"Build Boot ROM...".
2.2 the "Build Boot ROM" window will popup, in the "Select a BSP:" column
choose the "wrSbc405gp", and in the "Select an Image to build:" column
choose "bootrom_uncmp.hex" and press the "OK" button.
2.3 After the build process will finish successfully (You will see "Done" in
the "Build window" without error), you will have the bootrom_uncmp.hex in
your BSP directory "$(WIND_BASE)/target/config/wrSbc405gp".3. Programming bootrom_uncmp to SBC405GP FLASH:
If you are using visionCLICK please follow the instruction in section 3.1
If you are using SingleStep please follow the instruction in section 3.2
If you are using VisionXD please follow the instruction in section 3.33.1 Using visionCLICK:
3.1.1 Install the visionPROBE II or visionICE II and power it on.
Connect the JTAG interface cable from the visionPROBE II or
visionICE II into the SBC405GP board JTAG (JP12 The JTAG Port)
connector.Once all the connections have been made, power up the SBC405GP
board and start the visionCLICK executable on the host.3.1.2 Configure the visionCLICK project:
The "Welcome To visionCLICK" window will appear .In this window
press on the "Configure" button, This will invoke "PROJECTS/LOAD"
window. In this window press on the + left to the
"PowerPC_C_Demo.prj".This will show you the project configuration.
Point with the mouse cursor on the "Microprocessors" option and
press the right button and choose the type of CPU you have on your
board. For example: "PowerPC->IBM40x->405GP" . Verify that the
"Target Control" option point to visionPROBE for visionPROBE II or
visionICE for visionICE II, Also switch to the "Communications"
TAB and verify that the "Normal Port/Rate" & "Download Port/Rate"
suite your connection. for example: "LPT1" for visionPROBE II.
Now press the "Save" button at the bottom of the window and after
it on the "Activate" button.3.1.3 Program visionPROBE II / visionICE II with the proper register
setting for the SBC405GP board:Go to the "Tools" menu and select the
"Log Output/Playback Scripts" option. The "Record / Playback"
dialog box will popup. In this dialog box go to the
"Playback Commands From File" group and press on the "Browse"
button. Navigate your self to the location of the following
register file: "sbc405gp.reg", the file located in the
visionCLICK installation. After choosing the register file press
on the "Open" button to confirm the selected reg file. You will
return back to the "Record / Playback" dialog box. Now press on
the "Start" button located in the same group. In the "Terminal"
window you can see that the visionCLICK is running the script.
When visionCLICK will finish the playback you will get back the
">BKM>" or the ">ERR>".3.1.4 Get into Background Mode:
Execute the "IN" command to reset the board and initialize it with
the register setting..CS
IN
.CSThis command is the reset command to initialize the board.
3.1.5 Enabling the TRPEXP option in visionCLICK:
Execute the "CF TRPEXP YES" command in the "Terminal" window,
after you get back the ">BKM>" prompt execute the "IN" command to
reset the board.** NOTE: If the "TRPEXP" option is set to "NO" the Flash erasing &
programming will fail with timeout. On the other hand to
run VxWorks using visionPROBE II/visionICE II "TRPEXP"
option need to be set to "NO".3.1.6 Converting the bootrom_uncmp.hex to bootrom_uncmp.bin:
3.1.6.1 In visionCLICK, choose "Convert Object Modules" from the
"Tools" menu. The "CONVERT BINARY AND SYMBOL OBJs" dialog
box will pop up.Select "All Files" in the "Files of Type"
box. Go to the "Select Input Object Module To Convert"
group and navigate to the file "bootrom_uncmp.hex"
located in:
"$(WIND_BASE)/target/config/wrSbc405gp/bootrom_uncmp.hex"3.1.6.2 In the group "Binary Downloadable Objects Modules" check
the "Create Flat BIN File For Flash Programming".
"In Range Of 0x" editbox, enter 0 for the start address,
and in the "To 0x" editbox, enter "FFFFFFFF".3.1.6.3 Make sure that all the other check box are unchecked.
Press the "Convert" button. Close the terminal window
when the conversion completes.3.1.7 Programming the SBC405GP Flash:
In visionCLICK, select "Program Flash Devices" from the Tools
pull-down menu. This will invoke the "TF FLASH PROGRAMMING"
window. If you are not using visionCLICK, you can also invoke
this window using the "visionICE Utilities Panel" and follow the
steps below:3.1.7.1 Click the "Select" in the "Flash Card or PC Host File
Name and Path" group. The "CHOOSE A FILE FROM HOST PC"
dialog box will popup. In the edit box enter the full path
to the location of the "bootrom_uncmp.bin", or use the
"<--Browse" button to browse to the file location. Go to
the "+/- Bias" group and enter the number "FFE00200" in
the edit box. Now click the "OK" button, this will bring
you back to the "TF FLASH PROGRAMMING" dialog box.3.1.7.2 In the "Programming Algorithm" group in, the edit box
press on the "Select" button, and select one of the
following Flash devices:For the 16MB Flash: "INTEL 28F640Jx (4096 x 16) 2 Devices"
3.1.7.3 Set the proper address of the Flash to "FFE00000", check
the "Erase To" radio button, and set the end address of
the FLASH to "FFFFFFFF".Set the "Available RAM Workspace" setting to "00000000",
set the "Bytes Of Target RAM Required" to "60000".3.1.7.4 Press the "Erase and Program" button.
3.1.7.5 Now the Flash memory is programmed with the new boot
program.3.2 Using SingleStep for vision:
3.2.1 Install the visionPROBE II or visionICE II and power it on.
Connect the JTAG interface cable from the visionPROBE II or
visionICE II into the SBC405GP board JTAG (JP12 The JTAG Port)
connector.Once all the connections have been made, power up the SBC405GP
board and start the SingleStep for vision executable on the host.3.2.2 Configure the SingleStep project:
3.2.2.1 Go to the "File" menu and choose the
"Start Debug Session..." .3.2.2.2 The "Debug" dialog box will popup, In the "Connection" tab
choose the visionPROBE option & the correct LPT port if
you are using visionPROBE, or visionICE & enter the
emulator IP address if you are using visionICE.3.2.2.3 In the "Processor" tab choose the "405GP".
3.2.2.4 In the "Register" tab choose the option
"Use vision-style register window with REG file" and then
browse to the location of the file "sbc405gp.reg" and
choose it. The "sbc405gp.reg" file should be in the
SingleStep directory.3.2.2.5 In the "File" tab choose the "Debug without a file"
option.3.2.3 Get into Background Mode:
3.2.3.1 Now in the "File" tab press OK.
3.2.3.2 Now should get the "Debug Status" dialogbox and in the
"Debug Session" field you should have in green
"Started Successfully", press the "Close" button.3.2.3.3 Now go to the "Command" button in the toolbar and press on
it. The "Command" Window will popup, the prompt in the
window will be "SingleStep". Bring the mouse cursor above
the "Command" window and press the right button. A menu
will popup, choose the "VisionShell(vsh)" option. Now the
prompt in the window will be ">BKM>". If the prompt is
">ERR>" execute the "IN" command to reset the board and
initialize it with the register setting..CS
IN
.CS
This command is the reset command to initialize the board.
After you got the ">BKM>" prompt again continue with the
instruction in the next section.3.2.4 Converting the bootrom_uncmp.hex to bootrom_uncmp.bin:
3.2.4.1 Go to the menu and choose "Tools" and
"Vision Flash Utility..." .3.2.4.2 The "Flash Programming Window" will popup. Go to the
"Files" tab, press the "Convert" button.3.2.4.3 The "File Convertion" window will popup. In the
"Enter new start address" edit box type "0x0" and in the
"Enter new end address" edit box type "0xFFFFFFFF".3.2.4.4 Now press the "Convert" button. After the convert operation
finished, you will see it in the "Convert Result" section
press the "Close" button.3.2.5 Programming the SBC405GP Flash:
3.2.5.1 Go to the menu and choose "Tools"->
"Vision Flash Utility...". In the
"Flash Programming Window" window. Go to the
"Configuration" tab, & choose the following Flash device:For the 16MB FLASH: "INTEL 28F640Jx (4096 x 16) 2 Devices"
In "Flash Bank" group for the "Start:" enter "FFE00000" .
In the "RAM Workspace" group for the "Workspace Start at:"
enter "00000000" and for the "Workspace Size:" enter
"60000".3.2.5.2 Now switch to the "Files" tab and press the "Add" button.
The open dialogbox will popup, browse to
"$(WIND_BASE)\target\config\wrSbc405gp "bootrom_uncmp.bin" or "bootrom.bin" file. Now after
getting back to the "Files" tab you will see the full path
to the selected file in the "Binary Files" group. Move the
mouse curser above the line that showing the full path in
the "Binary Files" group and press the right button to
mark this line. Now press the "Toggle Enable" button to
select this binary file. Make sure that the line is still
marked, and press the "Edit" button on the right. The
"File Edit" dialog box will popup. In the
"Enter new start address" edit box enter "0xFFE00200" and
press the "OK" button.3.2.5.3 Now go to the "Program" tab and press the "Erase/Program"
button. After the process finished continue to the next
step.3.3 Using visionXD:
3.3.1 Install the visionICE II and power it on. Connect the JTAG
interface cable from the visionICE II into the SBC405GP board
JTAG (JP12 The JTAG Port) connector.Once all the connections have been made, power up the SBC405GP
board and start the visionXD executable on the host.
The VXDHOME environment variable should be set to the base
of the visionXD installation tree, and the PATH should include
$VXDHOME/bin.3.3.2 Configure visionXD:
Select "Configure Global Settings..." from the Tasks menu.
This will open the Configuration Editor.In the Communications section, enter the IP address of the
visionICE II.In the Target section, select PPC405GP as Processor and VxWorks
as RTOS.3.3.3 Get into Background Mode:
Select "Initialize" from the Target menu. This resets the board.
3.3.4 Enabling the TRPEXP option in visionXD:
Select "Terminal..." from the Tasks menu.
Execute the "CF TRPEXP YES" command in the "Terminal" window,
after you get back the ">BKM>" prompt execute the "IN" command to
reset the board.** NOTE: If the "TRPEXP" option is set to "NO" the Flash erasing &
programming will fail with timeout. On the other hand to
run VxWorks using visionICE II "TRPEXP"
option need to be set to "NO".3.3.5 Converting the bootrom.hex to bootrom.bin:
3.3.5.1 In a host terminal window, with the environment set
according to sec. 3.3.1, change to the directory
containing the bootrom.hex file, for example:cd $WIND_BASE/target/config/wrSbc405gp
3.3.5.2 Execute the "convert" program:
convert -s bootrom.hex -a bootrom.bin
3.3.6 Programming the SBC405GP Flash:
In visionXD, select "Program Flash..." from the Tasks menu.
This will open the Flash Programmer.3.3.6.1 Select "Target Flash" as Method.
3.3.6.2 In "File to Program", select Source as Host File System.
In the Name: edit box enter the full path
to the location of the bootrom.bin file, or use the
folder-icon button to browse to the file location.
In the "+/- Bias" edit box enter the number 0xffe00200.3.3.6.3 In "Device Configuration, Start Address, and
Optional End Erase Address", select Devices as
"INTEL 28F640Jx (4096 x 16) 2 Devices". Set the
Start Address to 0xffe00000 and select the End Address
as Automatic.3.3.6.4 In "Target RAM Workspace", set Start Address to 0 and
Size to 60000.3.3.6.5 Click the "Erase and Program" button. The erase
operation should take about 10 seconds. The program
operation should take about 2 minutes.4. Running the VxWorks Boot ROM program:
** NOTE: To run VxWorks using visionPROBE II/visionICE II the TRPEXP option
need to be set to NO.4.1 Disconect visionPROBE II or the visonICE II if it still connected to the
board, because it still connected to the board in some case it can stop
the processor at the first instruction.4.2 Connecting the Ethernet channel and the serial channel:
4.2.1 First, connect the supplied serial cable with the board. On
one said connect the RJ11 connector to the RS232 (JP2) port on
the SBC405GP board, and on the other said use the RJ11 to 9/25 Pin
addapter to connect it to your host. The UART devices is set as
follow: 8 data bits, 1 stop bit, hardware handshaking, and parity
disabled. The serial console (9600 bps).4.2.2 Second, connect a standard Ethernet cable to the the RJ45 (JP10)
connector on the SBC405GP board.4.3 Launch a terminal program on the host said, and configures it according
to the following details: 8 data bits, 1 stop bit, hardware handshaking,
and parity disabled. The serial console (9600 bps).4.4 Now to execute this new boot program turn the board off,and on. and you
should get the vxWorks boot count down on the terminal window. Press any
key to stop the count down. Now follow the instruction in the
instructions in the "Getting Started" chapter of the
"VxWorks Programmer's Guide." for more detail how to configure vxWorks.
bootrom_uncmp.bin & bootrom.bin are provided with this BSP. The bootrom is configured to a ROM base address of 0xFFE00200, the address space between 0xFFE00000 - 0xFFE001FF is used to emulate NvRam on the Flash, the BSP also configured to use the PPC405GP internal 10/100BaseT Ethernet controler as default boot device and the RS232 as console device.
The following section will explain how to launch VxWorks using visionWARE as a boot loader. Please follow the steps below:Note: Before using vsionWARE you need to verify that visionWARE is programmed
to you FLASH. If visionWARE is not exist on your FLASH, please see
"Programming bootrom_uncmp to SBC405GP FLASH using visionCLICK/SingleStep"
section how to program the SBC405GP Flash, and instead of programming the
"bootrom_uncmp.bin" program the "vWARE.bin" file.1. Connect your SBC405GP serial channel (RS232) to a host running terminal
program at 9600 baud rate (For example "HyperTerminal") using the
supplied serial cable.2. Connect your SBC405GP 10\100Base-T (The Ethernet port on the board JP10)
port to a network hub.3. Open TFTP server and point to the location of the vxWorks.bdx file. If
you want to use the TFTP server that is supplied with visionWARE, go to
the visionWARE directory on your host, inside the visionWARE root
directory you will find "tftp" directory that contain application called
"tftpd32.exe" . Run this application and the TFTPD32 window will popup.
In the TFTPD32 window press on the "Settings" button. This will invoke
the "Tftpd32: Settings". Go to the "Base Directory" group and inside the
edit box type the full path to your vxWorks image, or use the "Browse"
button to navigate to there.4. Power up your SBC405GP and press any key within 1 seconds from the
serial terminal to abort the boot script. This will display a ">BKM>"
prompt.5. Type the "shell" command and press enter. Now you should get the
following line: "Command Channel = 0: serial >" Press enter.6. Next line will be: "Boot Delay (seconds) = 6 >" . Here you need to
specify the desired delay value and press enter.7. Next line will be: "Boot Script = >" . Here you need to give the boot
script command. Please type the following:"load \host\vxWorks.bdx!launch 10000"
is the host name, and press enter.
Note(s):
** It is very important to keep the same space between the
"load" command and the host name "\host".** The host name should be the same as specified in the
"Remote System 1 Name" line.8. Next line will be "MAC Address = 00-A0-11-22-23-E8 >" . If you want to
change the target MAC address, type it now and press enter, else press
just enter.9. Next line will be "IP Address = 0.0.0.0 >" . Type your target IP
address. For example: 172.16.12.12 and press enter.10. Next line will be "Subnet Mask = 0.0.0.0 >" . If you want to use subnet
mask, type it now and press enter, else just press enter.11. Next line will be "Default Gateway = 0.0.0.0 >" . If you want to use
default gateway, type it now and press enter, else just press enter.12. Next line will be "Remote System 1 Name = >" . Here you need to type the
same host name you specified in the "Boot Script" line.13. Next line will be "Remote System 1 IP = >" . Here you need to type your
host IP address. For example: 172.16.18.33 and press enter.14. Next line will be "Remote System 2 Name = >" . Just press enter.
15. Next line will be "Remote System 3 Name = >" . Just press enter.
16. Next line will be "Remote System 4 Name = >" . Just press enter.
17. Next line will be "Command Channel = 0: Serial >" . Just press enter.
18. Now you will get the following message:
Saving changes will generate a reboot.
Save Changes (y/n)?Press y to save the changes.
19. Now the changes are saved and the board will restart visionWARE and boot
vxWorks, after a few seconds you will get the following messages:Wind River visionWARE v2.00 EAR HSI PPC405 Chameleon Board Wind River HSI +1(781) 828 5588 Build #4, 05/14/01 16:14:45 MAC : 00-A0-11-22-234-E8 IP : 172.16.12.12 Type "shell" to set IP and/or MAC addresses Type "help" to see available commands Press a key in the next <6> seconds to preempt boot script Booting from script... load \\host\vxWorks.bdx!launch 10000 >RUN>Attached TCP/IP interface to emac unit 0 Attaching network interface lo0... done. NFS client support not included. VxWorks Copyright 1984-1998 Wind River Systems, Inc. CPU: IBM PowerPC 405GP Rev D - WindRiver. SBC405GP VxWorks: 5.5 BSP version: 1.2/6 Creation date: Nov 22 2001 WDB: Ready.For more information regarding visionWARE boot services and the visionWARE development kit, please refer to the visionWARE manuals, located on the CD that was shipped with your board.
The supported boot device(s) is(are):
emac - 100\10BaseT Ethernet
or
fei - 100\10BaseT Ethernet
This section describes the support and unsupported features of the SBC405GP
The following features of the SBC405GP board are supported in this release:
- IBM PPC405GP Rev D only.
- MMU on the PPC405GP processor.
- System Timer (uses 405GP PIT hardware timer)
- Auxiliary Timer (uses 405GP FIT hardware timer)
- Watchdog Timer (uses 405GP WDT hardware timer)
- Both 405GP integrated 16550-style serial ports
- 405GP integrated Universal Interrupt Controller (UIC)
- MAL/EMAC (integrated Memory Access Layer and 10/100 Ethernet MAC) or
- Intel 82557/9 Ethernet controller (using fei82557End driver)
- 64MB SDRAM DIMM
- 16MB On Board FLASH
- 405GP PCI controller
- Saving boot parameters on Flash
- Support for the optional Wind River FPGA card (Proteus)
- SDRAM autoconfiguration
This section documents the details of the device drivers and board hardware elements for the SBC405GP.
This bsp provides the following chip drivers:
evbNs16550Sio.c - 16550 serial driver. ppc405Timer.c - timer driver for the PPC405GP. sysNvRam.c - Emulating NvRam on Intel 28F640J3 Flash. i28F640J3Mem.c - Intel 28F640J3 Flash routines. uicIntr.c - on-chip Universal Interrupt Controller. ibmEmacEnd.c - IBM 405GP integrated Ethernet controller.It also provides DCR access routines for the following functional units:- IBM DMA controller - IBM external bus controller - IBM Memory Access Layer (MAL) - IBM SDRAM controller - IBM Universal Int Controller (UIC)The BSP configures On Chip NS 16550 competible UART to implement a console device and the IBM EMAC as an Ethernet.
Memory Map from CPU point of view Start Size Access to --------------------------------------------------------------------- 0x0 64MB (min) SDRAM SODIMM 0xFF000000 16MB On Board FLASH 0xEF600000 4KB UART + OPB + IIC (Registers) 0x80000000 ---- PCI non-prefetchable memory 0xE8800000 100MB PCI 32 bit IO space 0xE8000000 4KB PCI 16 bit IO space
This BSP supports MMU on the PPC405GP processor. Memory is mapped using a fixed page size of 4K.
The sysPhysMemDesc[] array in sysLib.c is used to initialize the Page Table Entry (PTE) array used by the MMU to translate addresses with single page (4k) granularity. Address translations for local RAM, and local PROM/FLASH are set here. PTEs are held in a 2-level page table. There is one Level 1 page table and several Level 2 page tables. The size of the Level 1 table is 4K and the size of each Level 2 page table is 8K. Each Level 2 table can map upto 4MB of contiguous memory space.
For the following memory map we can calculate the page table size required as follows:
Memory Area Address Range Mapped Size Number of Level 2 pages Local Memory 0 - Ram size 32MB 8 PCI Memory 0x80000000-0x83FFFFFF 64MB 16 PCI IO Regn 1 0xE8000000-0xE800FFFF 64K 1 PCI IO Regn 2 0xE8800000-0xE88FFFFF 1MB 1 PCI CFG 0xEEC00000-0xEEC00FFF 4K 1 PCI IACK 0xEED00000-0xEED00FFF 4K 0 * PP Bridge 0xEF400000-0xEF400FFF 4K 1 UART IO Space 0xEF600000-0xEF600FFF 4K 0 * Flash 0xFF000000-0xFFFFFFFF 16MB 4
* included in previous L2 pageTotal # of L2 pages = 32
Total Memory Required for page table = 32 * 8 + 4 = 260 K.By default, to increase performance the instruction MMU (IMMU) is turned off. In this case, instruction cacheability is controlled by ICCR (which by default is set to cache all RAM). The IMMU can be re-enabled by defining USER_I_MMU_ENABLE in config.h.
This BSP emulate NvRam via a the On Board FLASH device. There are a few user parameters associated with this device. The parameters are located in the "config.h" file and are:#define ETHERNET_ADR_SET /* (used in bootConfig.c to enable 'N' command) */The ETHERNET_ADR_SET is a macro that indicates the MAC address is stored in NVRAM and alterable via the N bootrom command.
The Enhanced Network Driver (END) used with the integrated EMAC Ethernet core is "ibmEmacEnd" or the Intel 82559 (FEI) PCI Ehternet controller. The EMAC & FEI works at either 10Mbps or 100Mbps. EMAC gets the results of the PHY's auto-negotiation process over the MII interface.Since MAL is a Processor Local Bus (PLB) master, its accesses to system memory are unknown to the processor's L1 cache because there is no hardware enforced cache coherency in the 405GP. The ibmEmacEnd driver maintains coherency for both buffer descriptors and buffers.
The following are not supported in the current driver:
- TX channel 1
- wake-on-LANThe Ethernet hardware address is configurable at run-time. The first three bytes of the address are always assumed to be 0x00A01E (Wind River) and the last three bytes are configurable and stored in NVRAM at address 0xFFE001F0.
If desired, an Intel 82559 PCI Ethernet card can be plugged into the SBC405GP board. This controller uses the fei82557End driver provided with VxWorks.
The SBC405GP boards do not have a unique Ethernet hardware address assigned to each board. A unique address is absolutely necessary if the user wishes to connect the board to a network. Thus, the user must provide a suitable 6 byte Ethernet address for each board used on a network. The first 3 byte are Wind River specific and they specified in "config.h" the last 3 byte are use specific and thet specified in the NvRam and can be changes by using the N option in the bootrom prompt or from the shell.1. Changing the first three bytes:
The first three bytes (0x00, 0xa0, 0x1e) are a Wind River specific prefix
that should be kept as-is. If for some reason you need to change them, in
"config.h" change the following macros:#define ENET_DEFAULT 0x00A01E00
If these bytes need changing (they often will not), a new boot ROM must be
burned, and a new image must be built.2. Changing the last three byts:
The last three bytes of the Ethernet Address can be specified at the
bootrom prompt (N command) or at the shell prompt. The last three bytes of
the Ethernet address are stored in the on board NVRAM.2.1. Changing the last three bytes from the bootrom prompt:
This option will able you to change the last three bytes from the
bootrom prompt. To use this option, open the console window (for
example: "Hyper terminal") and when the bootrom banner appear and the
countdown start, press any key, when you get the "[VxWorks Boot]"
prompt, press N and follow the instructions.2.2. Changing the last three bytes from the shell prompt:
This option will able you to change the last three bytes from the
shell prompt. To use this option follow those step:1. Boot VxWorks.
2. Execute the following command from the shell:
If the Ethernet address last three bytes are: 11 22 33
sysLanIbmEmacEnetAddrSet 0x00, 0x00, 0x00, 0x11, 0x22, 0x33
The BSP "as supplied" is configured for the EMAC driver, but it can also support the FEI driver that is used for Intel 82557, 82558, and 82559 devices. To configure the BSP for the FEI driver instead of the EMAC:1. In "config.h" change the following line:
FROM:
#define BOOT_DEVICE EMAC_ENDTO:#define BOOT_DEVICE FEI_END
2. Now rebuild the bootrom and create a new VxWorks image project and build
it.** Don't forget to change the device name to "fei" in the "boot device"
line in the bootrom.
The BSP configures to use the 16MByte On Board Flash. This is the only Flash on the board.
The default configuration of the serial ports are 9600bps, 8 data bits, no parity, 1 stop bit.
This VxWorks SBC405GP board uses a simple 3 wire connection and standard phone jacks where pin 1 = RIN, pin 2 = TOUT, pin 3 = NC, and pin 4 = GND.
There is no SCSI interface on this board.
The board contain one 32-bit address, 32-bit data; complies with PCI Local Bus Specification, Revision 2.1 the PPC405GP is the PCI bridge. The current version of the BSP is supporting the pciConfigLib & pciAutoConfigLib.
The wrSbc405gp BSP support the Wind River FPGA card. This card is an optional product sold separately. The support is done by supplying the user a load routine that load the FPGA. The Wind River FPGA card can be connected to the 405 External Bus or to the PCI bus by connecting it to the PMC slot, currently only the 405 External Bus option is supported. To add the support for the card the user need to plug the card to the SBC405GP External Bus connectors those connectors are marked on the board as "CUSTOM Mezzanine SLOT" and to change the following line in "config.h"From:
/* Wind River FPGA card support */ #undef INCLUDE_WR_FPGA_CARDTo:
/* Wind River FPGA card support */ #define INCLUDE_WR_FPGA_CARDAnd re-build the bootrom and the vxWorks image. This will initialize the necessary CS and map the card in the MMU table. One of the simple option to load the FPGA is by using the Target Server File System (TSFS), to do this make sure that "INCLUDE_WDB_TSFS" is defined in your vxWorks image, this is for the WDB target server file system. Done forget to enable to Read/Write permission the target server file system in the target server configuration.Here is example how to load the FPGA from the WindSH:
-> sysProteusLoad ("/tgtsvr/filename.bit")
The following images are delivered with the wrSbc405gp BSP:
bootrom bootrom.hex vxWorks vxWorks.st
Only bootrom_uncmp, bootrom & vxWorks have been tested.
This section describes miscellaneous information that the user needs to know about the BSP.
To use visionPROBE II/visionICE II with BSP code or VxWorks application code, the following "CF" option need to be set:
CF TRPEXP NOTo do this, go to the visionCLICK/visionXD terminal window and type the command "CF TRPEXP NO" and press enter, then type "IN" and press enter.
The PPC405GP reset vector is located at 0xFFFFFFFC. That enable us to locate the boot code anywhere in the Flash. The default location of the boot code is in the begining of the Flash at 0xFFE00200 (The first 0x200 is used for NvRam). if you desire to move it you need to change the following:1. Changing the macro "ROM_BASE_ADRS" in the "config" reflect the new address.
2. Changing the macro "ROM_TEXT_ADRS" in the "Makefile" reflect the new
ROM_BASE_ADRS + NV_RAM_SIZE for example:If the new ROM_BASE_ADRS = 0xFFF80000 & NV_RAM_SIZE = 0x200 then the new
ROM_TEXT_ADRS should be equl to 0xFFF802003. Programing a new branch absolute command at address 0xFFFFFFFC, the original
branch command that comes with the BSP is "ba FFE00000"
There are errata in the 405GP processor which affect the operation of this Board Support Package. You should familiarize yourself with them. A current 405GP errata list is available from the PowerPC Technical support group (ppcsupp@us.ibm.com).
N/A
Tornado User's Guide: Getting Started, VxWorks Programmer's Guide: Configuration, VxWorks Programmer's Guide: Architecture Appendix
Please refer to the following documents for further information on the SBC405GP board.
PowerPC 405GP Embedded Processor User's Manual SBC405GP User's Manual .