VxWorks BSP Reference : walnut
walnut - IBM PPC405GP EVB
This reference entry provides board-specific information necessary to run VxWorks for the walnut (IBM PPC405GP) BSP. Before using a board with VxWorks, verify that the board runs in the factory configuration by using vendor-supplied ROMs and jumper settings and checking the RS-232 connection. This BSP supports the PowerPC 405GP Rev D and Rev E parts. Rev B and Rev C support is deprecated; support remains as in original release, but has not been validated nor upgraded for this release. Rev A parts are no longer supported with this release.
The IBM 405GP Evaluation Board uses a single VxWorks-supplied AMD Am29F040 ROM (total 512KB). Install the ROM as follows:
The BSP supports the NVRAM (Dallas Semiconductor DS1743) on the walnut board. The boot parameters will be preserved when the system is powered off.
ROM Socket - U27 To load VxWorks, and for more information, follow the instructions in the Tornado User's Guide: Getting Started.
Not applicable.
The following features are supported in this release:
- MMU on the PPC405GP processor (MMU_BASIC only).
- System Timer (uses 405GP PIT hardware timer)
- Auxiliary Timer (uses 405GP FIT hardware timer)
- Watchdog Timer (uses 405GP WDT hardware timer)
- Both 405GP integrated 16550-style serial ports
- 405GP integrated Universal Interrupt Controller (UIC)
- MAL/EMAC (integrated Memory Access Layer and 10/100 Ethernet MAC)
- 405GP PCI controller
- AMD 79C97x family of Ethernet controller (using ln97xEnd driver)
- Allied Telesyn 2450T adapter (AMD 79C970) has been tested
- Allied Telesyn 2700TX adapter (AMD 79C972) has been tested
- other adapters with the same AMD controller may also work.
- SDRAM autoconfiguration (the default 32MB SDRAM DIMM can be replaced with
up to a 128MB DIMM) using IIC to read the DIMM SEEPROM
- ECC SDRAM
- NVRAM (Dallas Semiconductor DS1743)
- Real-time clock (Dallas Semiconductor DS1743) using ds1643rtc.c driver
- JTAG RISCWatch bootrom flash programming tool
This section documents the details of the device drivers and board hardware elements.
The chip drivers used by this bsp are:evbNs16550Sio.c - 16550 serial driver
ppc405Timer.c - timer driver for the PPC405GP
byteNvRam.c - generic non-volatile RAM driverThis bsp also provides the following chip drivers:
d1643RTC.c - RTC DS1643 real time clock driver
uicIntr.c - on-chip Universal Interrupt ControllerIt also provides DCR access routines for the following functional units:
- IBM DMA controller
- IBM external bus controller
- IBM Memory Access Layer (MAL)
- IBM SDRAM controller
- IBM Universal Int Controller (UIC)
This BSP supports MMU on the PPC405GP processor. Memory is mapped using a fixed page size of 4K.
The sysPhysMemDesc[] array in sysLib.c is used to initialize the Page Table Entry (PTE) array used by the MMU to translate addresses with single page (4k) granularity. Address translations for local RAM, memory mapped PCI bus, memory mapped IO space and local PROM/FLASH are set here. PTEs are held in a 2-level page table. There is one Level 1 page table and several Level 2 page tables. The size of the Level 1 table is 4K and the size of each Level 2 page table is 8K. Each Level 2 table can map upto 4MB of contiguous memory space.
For the following memory map we can calculate the page table size required as follows:
Memory Area Address Range Mapped Size Number of Level 2 pages Local Memory 0 - Ram size 32MB 8 PCI Memory 0x80000000-0x83FFFFFF 64MB 16 PCI IO Regn 1 0xE8000000-0xE800FFFF 64K 1 PCI IO Regn 2 0xE8800000-0xE88FFFFF 1MB 1 PCI CFG 0xEEC00000-0xEEC00FFF 4K 1 PCI IACK 0xEED00000-0xEED00FFF 4K 0 * PP Bridge 0xEF400000-0xEF400FFF 4K 1 UART IO Space 0xEF600000-0xEF600FFF 4K 0 * NVRAM Space 0xF0000000-0xF0001FFF 8K 1 Flash 0xFFF80000-0xFFFFFFFF 512K 1
* included in previous L2 pageTotal # of L2 pages = 30
Total Memory Required for page table = 30 * 8 + 4 = 244 K.By default, to increase performance the instruction MMU (IMMU) is turned off. In this case, instruction cacheability is controlled by ICCR (which by default is set to cache all RAM). The IMMU can be re-enabled by defining USER_I_MMU_ENABLE in config.h.
The default configuration of the serial ports are 9600bps, 8 data bits, no parity, 1 stop bit.
The Enhanced Network Driver (END) used with the integrated EMAC Ethernet core is "ibmEmacEnd": Note that the boot device name is now "emac", rather than "ibmEmac". The EMAC works at either 10Mbps or 100Mbps. EMAC gets the results of the PHY's auto-negotiation process over the MII interface.
Since MAL is a Processor Local Bus (PLB) master, its accesses to system memory are unknown to the processor's L1 cache because there is no hardware enforced cache coherency in the 405GP. The ibmEmacEnd driver maintains coherency for both buffer descriptors and buffers.
The following are not supported in the current driver:
- wake-on-LANIf desired, an AMD 79C97x PCI Ethernet card can be plugged into the Walnut board. This controller uses the ln97xEnd driver provided with VxWorks.
The Ethernet hardware address is configurable at run-time. The first three bytes of the address are always assumed to be 0x0004AC (IBM) and the last three bytes are configurable and stored in NVRAM at address 0xF0000500. To make the ethernet hardware address match the address printed on the decal attached to the Walnut board use the following example as a guide.
Ethernet hardware address on the Walnut board decal: 0004AC3E4B22
- boot VxWorks
- execute the following command from the shell:sysLanIbmEmacEnetAddrSet 0x00, 0x04, 0xAC, 0x3E, 0x4B, 0x22
The following Tornado bootrom file types are supported in this release. When using a Rev B or Rev C processor (which are deprecated), the patch405b.exe or patch405c.exe tool must be run on the entire ELF file. If a compressed bootrom is built, this is not possible.
bootrom_uncmp (405GP Rev B (deprecated), C (deprecated), D, E) bootrom_uncmp.hex (405GP Rev B (deprecated), C (deprecated), or D, E) bootrom (405GP Rev D, E only) bootrom.hex (405GP Rev D, E only) *** Note: Tornado bootrom builds are only supported through the command line makefiles -- do not use the Tornado IDE to build a boot ROM.
For PPC405GP_REVB (deprecated):
A batch file has been provided that will post-process the bootrom_uncmp file. After bootrom_uncmp is built, run the bootrrb.bat file. bootrrb.bat will modify bootrom_uncmp and will create a new bootrom_uncmp.hex.
For PPC405GP_REVC (deprecated):
A batch file has been provided that will post-process the bootrom_uncmp file. After bootrom_uncmp is built, run the bootrrc.bat file. bootrrc.bat will modify bootrom_uncmp and will create a new bootrom_uncmp.hex.
For PPC405GP_REVD_OR_E:
It is not necessary to post-process the bootrom files when using the 405GP Rev D or E processor.
For all processor revisions:
The standard uncompressed rom-resident project configuration is not supplied because it will not fit in the bootrom.
Create a bootrom by either
a) Rebuilding bootrom_uncmp.hex image and programming it into an
AMD 29F040 flash part using the following steps:- For PPC405GP_REVB
- make bootrom_uncmp
- run bootrrb.bat to create patched bootrom_uncmp.hex
(bootrrb.bat runs patch405b)- For PPC405GP_REVC
- make bootrom_uncmp
- run bootrrc.bat to create patched bootrom_uncmp.hex
(bootrrc.bat runs patch405c)- For PPC405GP_REVD_OR_E
- make bootrom_uncmp.hex or bootrom.hexb) If you have a JTAG RISCWatch processor probe, you can use
vx_rw_flash.cmd to program the flash part (see below).Connect a terminal or terminal emulator to the board (the 9 pin connector closest to the printed circuit board). Emulator parameters should be set to 9600bps, 8 data bits, no parity, 1 stop bit. Power-up the board, you should get an error because the default boot line in config.h is not 100% correct for your environment. Type in new configuration parameters using the bootrom menu (set boot device : emac). Your new configuration will be stored in the NVRAM.
An IBM RISCWatch based command file (vx_rw_flash.cmd) is provided that will program bootrom_uncmp.hex into the AMD Am29F040 flash part on the Walnut board. A RISCWatch JTAG processor probe and RISCWatch software version 4.5 or newer is required to use this utility.
The vx_rw_flash.cmd utility may need modification if you use a different SDRAM DIMM than was shipped with the Walnut board (see notes inside vx_rw_flash.cmd).
To use this utility,
- make bootrom_uncmp via the command line interface (not with the IDE).
- Run the bootrr_.bat batch file for the correct processor revision.
This step will create a patched version of bootrom_uncmp.hex
NOTE: The manual step of adding the branch instruction to
bootrom_uncmp.hex is NOT necessary if using this utility!
- Start IBM JTAG RISCWatch
- Make sure that the RISCWatch search path is set up to find files
in the Walnut BSP directory. One way to do this is to execute the
following RISCWatch command:
srchpath add c:\Tornado\target\config\walnut
- Execute the following command to start the flash programming process.
This example will place the bootrom_uncmp.hex file into the flash.
exec vx_rw_flash.cmd {"bootrom_uncmp.hex"}
To use RISCWatch with BSP code or VxWorks application code, the following
compiler options are necessary to get the proper debug information into
the executable.-gdwarf -O0
Only "Bootable applications" are supported in this release if you are using 405GP Rev B, or C. A bootable application consists of application code linked to a VxWorks image.
Both "Bootable applications" and "Downloadable applications" are supported if using 405GP Rev D or newer. A downloadable application is one that consists of one or more relocatable object modules that are downloaded and dynamically linked to a running VxWorks image. Downloadable applications are not supported with Rev B or C, because the patch405b.exe, or patch405c.exe tool cannot operate on relocatable objects.
Please see the "Terminology" sections of the Tornado User's Guide (Windows Version) 2.0 Edition 1 for more information on bootable applications and downloadable applications.
It is possible to automate the running of patch405b.exe, or patch405c.exe against the application image from the project facility GUI.
- Right click on the build ("default" for example)
- Select "Properties" from the context menu
- Select the "Macros" tab on the Properties window
- Select the "POST_BUILD_RULE" macro
- Set the value to "patch405b xxxxx" (REVB),
or "patch405c xxxxx" (REVC) where xxxxx is the name of the
image being built such as vxWorks or vxWorks.st.
This initial hardware sample is no longer supported.
There are errata in the 405GP Rev B chip that affect the operation of this Board Support Package. You should familiarize yourself with them. A current 405GP errata list is available from the PowerPC Technical support group (ppcsupp@us.ibm.com). To avoid 405GP Rev B errata a tool patch405b.exe has been included. This tool searches an ELF executable file (output of the linker) for certain patterns of instructions related to the above errata. If it finds a potential problem, it uses reserved space provided by patchtblb.s to create a "patch" which will avoid the errata. The patch table is allocated inside of sysALib.s because it includes patchtblb.s.
If you are using a 405GP Rev B be sure to define PPC405GP_REVB in config.h.
There are errata in the 405GP Rev C chip that affect the operation of this Board Support Package. You should familiarize yourself with them. A current 405GP errata list is available from the PowerPC Technical support group (ppcsupp@us.ibm.com). To avoid 405GP Rev C errata a tool patch405c.exe has been included. This tool searches an ELF executable file (output of the linker) for certain patterns of instructions related to the above errata. If it finds a potential problem, it uses reserved space provided by patchtblc.s to create a "patch" which will avoid the errata. The patch table is allocated inside of sysALib.s because it includes patchtblc.s.
If you are using a 405GP Rev C be sure to define PPC405GP_REVC in config.h.
There are errata in the 405GP Rev D chip that affect the operation of this Board Support Package. You should familiarize yourself with them. A current 405GP errata list is available from the PowerPC Technical support group (ppcsupp@us.ibm.com).
If you are using a 405GP Rev D be sure to define PPC405GP_REVD_OR_E in config.h.
There are errata in the 405GP Rev E chip that affect the operation of this Board Support Package. You should familiarize yourself with them. A current 405GP errata list is available from the PowerPC Technical support group (ppcsupp@us.ibm.com).
If you are using a 405GP Rev E be sure to define PPC405GP_REVD_OR_E in config.h.
Tornado User's Guide: Getting Started, VxWorks Programmer's Guide: Configuration, VxWorks Programmer's Guide: Architecture Appendix
Please refer to the following documents for further information on the Walnut board.
PowerPC 405 Reference Board Manual located at http://www.chips.ibm.com/products/powerpc/evalkits/405refbd.pdf (also on the PowerPC Embedded Processors, Cores, and Tools CDROM)
405GP_settings.pdf included in this BSP.