sandpoint - Motorola Sandpoint X2
This document describes the features of the Sandpoint reference host board with various PCI Processor Mezzanine Card (PPMC). The PPMC modules include the Unity (8240/8245/8241), Talos (745), Altimus (750/755/7400/7410), Gyrus (7441/7445) and the Valis (7450/7455). The various BSPs that provide support for these PPMC modules are the sp824x (8240/8245), sp7xx (745/750/755), sp74xx (7400/7410) , sp7450(7450), sp7455(7455), sp7445(7445) & sp7441(7441).
The board contains one PMC/PPMC - compatible slot, four PCI slots, Keyboard/mouse, floppy and IDE disk controllers. Sandpoint is intended for hardware and software development and evaluation purpose only, and is not intended for operation in commercial environments.
This BSP currently supports the X2 baseboard and the X3 baseboard in X2 compatibility mode.
The ROM device is an AMD AM29F040, or equivalent, residing in position U6. It is addressed from 0xFFF00000 to 0xFFF80000 (512K). The ROM resides on the ISA bus. 29F040 devices residing in socket U6 may be reprogrammed from the VxWorks kernel using the BSP routine sysUpdateFlash( ), from sysLib.c. This U6 socket is where the VxWorks bootrom should be installed into.
The BSP supports non-volatile RAM; thus boot parameters will be preserved whenever the system is powered off. Sandpoint incorporates an 8KB battery backed SRAM, which is organized as 8kbx8 and is used for the storage of system configuration information such as:
Passwords Boot record Global environment parameters Language data
To load VxWorks, and for more information, follow the instructions in the Tornado User's Guide: Getting Started.
The Sandpoint X2/X3 allow flexible operating configuration based on the settings of jumpers and switches on the base board and the PPMC modules. Note that the meaning of a jumper position or switch setting changes from revision to revision of the base board, as well as the PPMC modules. Refer to the Sandpoint System Documentation for correct interpretation of various configurations for the exact revisions of the base board and PPMC module in focus.
SNo. Jumper Function 1. J30,31,32 VIO selection jumpers 2. J33 Test Clock Input 3. J34 66MHz PCI Disable
SNo. Switch Function Mode 1 S1 Power On/Off Switch 2 S2 Reset Switch 3 S3, S4 Mode Selection Switch 1 4 S5 Input Inversion Switch Inverted Mode 5 S6 Winbond IRQ selection Switch Winbond IRQ shared with slot 2
If jumper J34 is installed, the PCI bus will operate at 33Mhz regardless of the status of the M66En signal. The PCI bus ordinarily selects 66MHz operation if (and only if) all PPMC and PCI devices installed support 66MHz clock rates; otherwise, the slower 33MHz rate is used. However, for testing purposes, this jumper may be used to evaluate slower bus clock rates. In addition, it may be needed for systems using the 66MHz-capable cards which also wish to use the Winbond or on-board I/O. Since these devices operate at 33Mhz only, and yet do not have an M66En pin to control clock selection, jumper J34 is required to force the PCI bus to operate at 33MHz.
Note that the default VxWorks kernel configuration uses the on-board COM1 port for console I/O and therefore requires jumper J34 installed.
Jumpers J30, J31, and J32 are used to set the I/O voltage signaling level for the PPMC card. As with PCI slots, the PPMC slot provides the ability to provide I/O on certain pins, and compatibility is maintened using keying methods (for PCI slots, a key is present in the slot, while for PPMC slots, a keying pin protrudes from the motherboard into the PPMC card). For flexibility in testing purposes, Sandpoint allows any types of VIO-Keyed board to be installed, with the proper VIO selected by jumper J30-J32.
Some PPMC cards, such as the PMC8240, are configured with active-high interrupt input when operated in the default configuration, which conflicts with PCI requirements. This is one example in which the MPC-8240 is not quite identical to an MPC603 + MPC106, so software moved as-is from the yellowknife to the PPMC8240 will find interrupts not to be working. The short term work around is to configure Sandpoint to invert the PMC interrupt signal; since this violates the specs, if intended only for a short term assistance, the correct solution is to program the EPIC of the MPC8240 to accept the correct polarity.
PPMC cards support four interrupt sources. When operating in modes 0 or 1, there are total five possible interrupt sources. When on board I/O is needed, it must share with or replace PCI devices in slot 2 or slot 3. Software must poll multiple sources to determine interrupt sources if both the slot and local I/O are needed; othewise, the slot can be left unused or used with non interrupting devices such as graphics cards. For default operation with vxWorks S6 should be set in a position towards the PPMC module so that it shares Winbond IRQ with slot 2.
Switches S3 and S4 should be set for mode 1. For this S3 should be in a position towards the PPMC module and S4 should be in a position away from the PMC module. The PPMC slot is the system controller and provides arbitration and interrupt control. The Winbond IDE disk controllers replace slots 1 and 2 (3.3V PCI slots). The 5V PCI slots 3 and 4 are available. The on-board I/O shares interrupts with slot 2 or 3.
SNo.| Switch | Function | Mode used _ 1 | S1 | ROMSEL | Primary ROM (29F040) is used for PCI boot option. 2 | S1 | ROM1WP | ROM1 may be read to or written from. 3 | S1 | Reserved | Reserved, has no function. 4 | S1 | FRCPCI33 | Force 33 MHz PCI Only. 5 | S1 | EXTCLK | Normal Clock Mode. 6 | S1 | SSCLK | Normal PCI Clocks. 7 | S1 | SSRNG | -3.75% modulation (Has relevance only if SW1-6 is OFF. 8 | S1 | PSON | Force Power ON always.
SNo.| Switch | Function | Mode used _ 1-2 | S2 | AMODE | FULL 3 | S2 | ILEGACY | Legacy Sandpoint 1/2 Interrupts Modes 4-5 | S2 | IMODE | Serial 6 | S2 | RMODE | ROM governs ROM/Flash access 7-8 | S2 | USER | User defined functions.
The Sandpoint motherboard is a "host" board, which accepts a PMC or PPMC card as well as having up to four PCI slots. The host board has the following features:
One PMC slot with PPMC, 64-bit and 66MHz extensions Switch-selectable operating modes Four PCI slots: two 5V/32-bit slots, two 3.3V/64-bit slots PCI slots support 33 or 66 MHz operation Two standard 16650-compatible ESD-protected serial ports IEEE 1284 parallel port Floppy disk port Two IDE ports PS/2 Mouse and keyboard connectors NVRAM and real-time clock (RTC) Advanced Power Controller ("soft on/off) LED monitors for critical functions Automatic sense of PCI bus speed (33 or 66 MHz) Flash EPROM for boot firmware Serial - two RS232 9pin serial devices System clock (PPC decrementer) Winbond WB83C553 as PCI to ISA Bridge Winbond WB83C553 as i8259 PIC Winbond WB83C553 as ATA EIDE controller Winbond WB83C553 as PS2 floppy disk controller Winbond WB83C553 as i8254 auxiliary clock DEC 21040 Ethernet Controller (PCI card) DEC 21140 Ethernet Controller (PCI card) DEC 21143 Ethernet Controller (PCI card) Intel 82557 Ethernet Controller (PCI card) Intel 82558 Ethernet Controller (PCI card) Intel 82559 Ethernet Controller (PCI card) AMD 79C970 Ethernet Controller (PCI card) AMD 79C971 Ethernet Controller (PCI card) AMD 79C972 Ethernet Controller (PCI card) 3Com 3C90x Ethernet Controller (PCI card)
The I/O subsystem does not support the following devices:
Parallel Port Keyboard and Mouse Ports National Semiconductor SuperIO Real Time Clock
None.
This section documents the details of the device drivers and board hardware elements.
The chip drivers included are:
w83553PciIbc.c - interrupt controller driver sysEpic.c - embedded interrupt controller driver ns8730xSuperIo.c - super IO device support i8250Sio.c - Intel 8250 UART driver i8254AuxClk.c - i8254 timer library (auxiliary clock) ppcDecTimer.c - PowerPC decrementer timer library (system clock) byteNvRam.c - byte-oriented generic non-volatile RAM library flashMem.c - 29F040 flash memory device driver. pciConfigLib.c - PCI Configuration Space Access Library pciConfigShow.c - PCI Configuration Space Display Library pciIntLib.c - PCI Interrupt Support Library pciAutoconfigLib.c - PCI Bus Auto-configuration Library fdcDrv.c - driver for PS2 floppy device controller(FDC) isaDma.c - I8237 ISA DMA transfer interface library ataDrv.o - ATA/EIDE HDD driver ataShow.o - ATA/EIDE HDD display if_dc.o - DEC 21x4x Ethernet LAN network interface driver dec21x40End.o - DEC 21x4x Ethernet LAN END driver fei82557End.o - Intel 82557, 82558, 82559 END driver ln97xEnd.o - AMD 79c97x END driver El3c90xEnd.o - 3Com EtherLink 3C90x END driver altiVecLib.c - AltiVec supportThe user configurable options are in config.h.
The following table describes the Sandpoint X2, using the CHRP memory mapping. While Sandpoint and the MPC107 also support PREP, CHRP is the only model tested. The following is the CHRP mapping as it relates to VxWorks.
VxWorks_rom Memory Image: _______________________________________________________________ | | | | | | | VxWorks_rom | | | | | | | ROM_TEXT_ADRS 0xFFF0 0100 | | | ROM_BASE_ADRS 0xFFF0 0000 | |___________________|___________________________________________| | | | | | | | Non allocated or | | | uninstalled RAM | | | | | | Top of RAM | LOCAL_MEM_SIZE 0x0100 0000 | |___________________|__________________________________________ | | | | | | | | | | | Zeroed out | | | by boot code | | | | | | | | | | | | | | |___________________|___________________________________________| | Top of RAM | RAM_HIGH_ADRS 0x0040 0000 | | containing vxWorks| | | (VxWorks code is | | | copied here from | | | ROM) | RAM_LOW_ADRS 0x0001 0000 | |___________________|__________________________________________ | | | | | | | | Zeroed out | | | by boot code | | | | Start Of Interrupt Vectors 0x0000 0100 | | | Physical Start Of RAM 0x0000 0000 | |_______________________________________________________________|
The Sandpoint does not currently support a shared memory driver.
The SandPoint BSP uses the MPC107 for PPMC750, PPMC755, PPMC7400 & PPMC7410 PPMC7450, PPMC7455, PPMC7441 & PPMC7445 and EPIC interrupt controller integrated in the MPC8240 micro-controller. Interrupt lines of PCI devices are connected to the EPIC module or the MPC107, while the interrupt lines of the serial port communications (COM1, COM2, AuxClock, Floppy, IDE) are connected to the Winbond chip.
Interrupt functions that initialize and support the interupt controller module are contained in the sysEpic.c and sysEpic.h files. Interrupt functions that initialize and support the serial communication are contained in the w83553PciIbc.c and w83553PciIbc.h files.
Internally, the Winbond IRQs are numbered from 0x10 to 0x20, while the EPIC/MPC107 IRQs are numbered from 0x0 to 0x4 (0x4 is not brought out on the PPMC). The EPIC interrupt priorities are assigned according to IRQ numbers.
COM1 is configured for IRQ4 and COM2 is configured for IRQ3 on the Winbond device. The winbond device is connected to IRQ2 of the EPIC module.
The two serial communication channels are defined in sp.h. The serial communications inclusion is determined by the macros INCLUDE_SERIAL and NUM_TTY in config.h. The supported baud rates depend on the i8250Sio.c driver. The BSP has been verified with the following baud rates:
115200, 57600, 38400, 19200, and 9600 baud.
______________________________________________________________________________________ | | | | | | | ____________________ | | | | | | | POWER PMC CARD | | | | ______________ | | | | | EPIC/MPC107 | | | | | |______________| | | | | | | | | | | | | | |_________|__________| | | IRQ 0 to | IRQ 3 PCI-SLOTS | | | | | | | | | | | | | | | | | | | | | | | | | | |=================|==|==|==| | | | | | | | | | | | | | | | | | | | | | | | | | | | | _________|__________ | | | Winbond 83553 | | | | PCI/ISA Bridge | | | |____________________| | | | | | IRQ 16 to |IRQ 31 | | | | | | | | | ON-BOARD I/O | | |_______________ | | | | | | | | | | | ______________|______________ | | | | | | | | | | | | | | COM-1 COM-2 FLOPPY IDE | | | | | | | | | | | | | | | |______________________________________________________________________________________|EPIC Interrupt Table
IRQ Priority Description 0 0 PCI Slot 1 1 1 PCI Slot 2, shared with Winbond IRQ 2 2 PCI Slot 3 3 3 PCI Slot 4 4 4 unused Secondary Interrupt Controller Winbond IRQ Table
The sysLib.c routine sysIntConnect( ) will call the appropriate intConnect routines, pciIntConnect( ) for PCI INTs, and intConnect( ) for all others. See also, sysEpic.[ch], w83553PciIbc.[ch].
IRQ Priority Description 16 2 i8254 Timer 17 2 unused 18 2 cascade 19 2 COM2 / ttyb / tyCo 1 20 2 COM1 / ttya / tyCo 0 21 2 unused 22 2 unused 23 2 unused 24 2 unused 25 2 unused 26 2 unused 27 2 unused 28 2 unused 29 2 unused 30 2 IDE controller 0 31 2 IDE controller 1
The default kernel configuration, as delivered, includes two serial communication ports com1 and com2, the Wind debugger WDB, and one "dc" (DEC 2114x) ethernet port.
Com1: is used for terminal display. The VxWorks banner, all VxWorks error messages, and all output generated by printfs in applications programs are displayed on this terminal. Either a vt100 type dumb terminal can be connected via a standard serial cable, or a vt100 type terminal emulator program on a PC can be connected via a null modem type serial cable.
Com2: is used for the WDB communication port. A null modem serial cable can be connected to the com2 port of a PC or UNIX machine. The Tornado program uses host shells to communicate to VxWorks on the target.
Com1 and com2 are interrupt driven drivers using the code in sysSerial.c. Com1 is configured for IRQ4 and com2 is configured for IRQ3. The two serial communication channels are defined in sp.h as COM1_ADR, COM1_INT_LEV, COM1_INT_VEC and corresponding com2 macros. sysLib.c calls the serial driver initialization functions during sysHwInit calling sysSerialHwInit( ) and sysHwInit2( ) and sysSerialHwInit2( ). The serial communications inclusion is determined by the macros INCLUDE_SERIAL and NUM_TTY in config.h.
This BSP does not support any SCSI devices at this time.
Ethernet communication is determined by the macro INCLUDE_NET in config.h.
Ethernet in the default version uses the DEC21140 ethernet chip set. It is implemented by either the if_dc driver or an END driver. Other cards supported are:
3COM 3C90x PCI Intel fei82557 DEC 21143 chipset AMD Ln97x
No VME bus is present on the Sandpoint X2.
PCI access is controlled via the MPC107 PCI Bridge/Memory Controller. Although this device supports three address mappings, the SandPoint board supports only two.
Address map A conforms to the PowerPC reference platform specification (PReP).
Address map B conforms to the PowerPC microprocessor common hardware reference platform (CHRP).
Some processor modules may have the address map (A or B) selection hardwired on the module, and need to be ordered for Address Map B. For details contact your Motorola sales office. The 7400/7410 MPMC rev X3 module allows switch selection of the address map via position 2 of SW2, which should be set to "off" to select Address Map B.
Address map A or B selection is displayed upon booting with the manufacturer-supplied DINK32 bootrom.
The function sysMemMapDetect( ) in sysLib.c detects the board configuration for the memory maps. This function sets the system PCI Configuration address and data address for Map B, MPC107_CFG_ADDR_CHRP and MPC107_CFG_DATA_CHRP, into the appropriate variables, sysPciConfAddr and sysPciConfData for the function sys107RegRead( ). Then it calls sys107RegRead which returns the value at that address. If the board is configured for Address map B (CHRP), the value returned will be the MPC107 vendor Id. If this is configured for Address map A (PREP), then the value returned will be garbage, i.e. will not be the correct Vendor Id. Thus, sysMemMapDetect( ) compares the returned value to the Vendor Id, and if it is not true, then the Map A PCI Configuration address and data addresses PREP_REG_ADDR and PREP_REG_DATA are placed into the variables, sysPciConfAddr and sysPciConfData.
A similar algorithm is used in romInit.s during startup in the code just prior to the function startMemInit( ). This code only detects Map A versus Map B for startup code, which is why it is necessary to do it again in sysMemMapDetect( ) after VxWorks (or bootrom) gains control.
PCI Autoconfig is supported and is used to configure the resources for each PCI device being used on the Sandpoint.
For more details, see MPC107 PCI Bridge/Memory Controller User's Manual.
Supported boot devices include:
fd=ctrl,drive - PS2 floppy device as boot device. (if INCLUDE_FD is defined)
`fd=<drive number>,<diskette type>' - Diskette drive number is one of: 0 = default; the first diskette drive (drive A:) 1 = the second diskette drive (drive B:) diskette type is one of: 0 = default; 3.5" diskette 1 = 5.25" disketteata=ctrl,drive - EIDE/ATA HDD as boot device. (if INCLUDE_ATA is defined)
`ata=<controller number>,<drive number>' - ATA/IDE drive controller number is one of: 0 = primary controller described in the first entry of the ataResources table 1 = secondary controller described in the second entry of the ataResources table drive number is one of: 0 = first drive on the controller 1 = second drive on the controllerNote: By default, with INCLUDE_ATA, vxWorks is set up for one ATA hard disk device on the primary ATA controller. The 2nd hard disk on the primary controller and the secondary controller are normally disabled to prevent timeouts. If you have multiple controllers and/or hard disks you must modify config.h ATA_DEV[x]_STATE values. See config.h.
dc - DEC 21040/21140/21143 network device (if PRIMARY_ENDTYPE == DEC_END_DEVICE in config.h for bootrom) lnPci - AMD 79C970/79C971/79C972 network device (if PRIMARY_ENDTYPE == AMD_END_DEVICE in config.h for bootrom) fei - Intel 82557/82558/82559 network device (if PRIMARY_ENDTYPE == FEI_END_DEVICE in config.h for bootrom) elpci - 3Com 3c90X network device (if PRIMARY_ENDTYPE == ELPCI_END_DEVICE in config.h for bootrom) sl - SLIP network device (if included in image)
The network support available for booting includes: bootp, ftp, tftp, slip, and rsh.
The sysLib.c routine sysUpdateFlash( ) will rewrite the 29F040 flash with data from a binary file filename.
This code allows the user to overwrite the flash device with data from file filename using the low level flash support routines sysFlashSet( ) and sysFlashGet( ) from src/drv/mem/flashMem.c. It writes data to the flash device via sysFlashSet( ), and verifies that the data was written correctly. Writes to flash are wrapped within taskLock( ) and intLock( ). The user should pass a binary bootrom file; for example to update the bootrom with a VxWorks BSP bootrom image:
% make bootrom.bin -> sysUpdateFlash ("hostname:/tmp/bootrom.bin") The flash has been updated without error. ->
The ROM is a 29F040B, or equivalent, in position U6. Building any of the following targets will create a Motorola S-record file suitable for downloading to most ROM programmers:
bootrom.hex vxWorks.st_rom.hex
Note that the make will abort if the image will not fit in the 512K ROM.
The Sandpoint hardware does not include an onboard ethernet controller. The user will need to supply a PCI ethernet controller card. The supported ethernet chip types include:
Device Vendor Bus NETIF SENS/END 21040 Digital PCI yes yes 21140 Digital PCI yes yes 21143 Digital PCI no yes 82557 Intel PCI no yes 82558 Intel PCI no yes 82559 Intel PCI no yes 79C970 AMD PCI no yes 79C971 AMD PCI no yes 79C972 AMD PCI no yes 3c90X 3Com PCI no yes
D-Link DFE-500Tx - Rev C6 (DEC 21140) (both netif and END drivers) D-Link DFE-500Tx - Rev C2 (DEC 21140) (both netif and END drivers) DEC EB143 - PCI Rev 2.0 (DEC 21143) (END driver only) Intel EtherExpress Pro100B PCI (82557 based) (END driver only) Intel EtherExpress Pro100+ PCI (82558 based) (END driver only) Intel EtherExpress Pro100+ PCI (82559 based) (END driver only) AMD PcNet-FAST Level One (AMC972 based) (END only) AMP RayLan 1001a PcNet-FAST (AMC972 based) (END only)
Delivered Objects in this version is
ataDrv.o - ATA/EIDE HDD driver
ataShow.o - ATA/EIDE HDD display
if_dc.o - DEC 21x4x Ethernet LAN network interface driver
dec21x40End.o - DEC 21x4x Ethernet LAN END driver
fei82557End.o - Intel 82557, 82558, 82559 END driver
ln97xEnd.o - AMD 79c97x END driver
El3c90xEnd.o - 3Com EtherLink 3C90x END driver
L1 cache locking is available for MPC8240, MPC750, MPC755, MPC7400 and MPC7410. The cache lock routine can be used to lock the entire data or instruction cache with a specified memory region.
L2 Cache is available for MPC750, MPC755, MPC7400, MPC7410, MPC7450, MPC7455 & MPC7441. Callback function pointers for L2 cache Global Invalidation, L2 Cache Enable, L2 Cache Flush and L2 Cache Disable are intialized in sysHwInit( ). Note: The L2 Cache was not behaving consistently on the MPMCGYRUS Rev X2
board on which the sp7445 bsp was tested. So the L2 cache has to
disabled for the sp7445 BSP by undefing INCLUDE_CACHE_L2 untill
the issue is resolved.
This feature is supported only on PPMC755 or PPMC7410. Part of the L2 SRAM can be configured as private SRAM, and can be mapped to physical address space. By default, INCLUDE_L2PM is defined for the sp755 BSP which installs 512K of L2 cache SRAM as a private L2 SRAM region beyond the local RAM region. Since the PPMC7400 and PPMC7410 shares the same BSP sp74xx, to enable L2PM support for the 7410, you need to use -DSP7410 in the Makefile. This can be done by commenting and uncommenting the EXTRA_DEFINE lines in the Makefile.
L2 cache locking is supported on MPC750, MPC755, MPC7400 and MPC7410. On these CPUs L2 is implemented as an unified cache. The L2 cache lock library can be used to lock data or instructions in the L2 cache.
support an altiVec sub-system that implements vector processing. Support for altiVec is now available, but an altiVec aware compiler must be used to create applications that use altiVec instructions. The altiVec support, can be enabled by defining INCLUDE_ALTIVEC in config.h
Note: Cache snooping is not supported in the present release.It can be enabled by defining SNOOP_ENABLE in config.h. When enabled, memory allocated via cacheDmaAlloc will have both snoop enable MMU flag, and cache flag turned on. This is not recommended for this release.
L3 cache is supported on MPC7450/MPC7455. The L3 Cache is implemented as a unified cache.
The Release Macro in the Makefile is defined asRELEASE = bootrom.hex vxWorks vxWorks.st
The following images can not be built.
vxWorks_rom ....................... image too big vxWorks.res_rom .................. undefined reference to RAM_DST_ADRS vxWorks.res_rom_res_low .... image too big bootrom_res .......................... undefined reference to RAM_DST_ADRS
The ROM resident images have not been tested.
PROBLEM #1:
Reading Device and Vendor Ids from PCI IDSEL 12 may cause the system to hang. A workaround solution is to skip this IDSEL when reading PCI devices. Example:
for (idsel = 0; idsel < 32; idsel++)
if (idsel == 12)
continue;
else
{
.......
}Switch S6 in shared slot 2 position does not appear to work if switches S3 & S4 are placed in MODE 0.
Slot numbers are incorrectly labelled in the documentation. The slot numbers from the PPMC outward are 2,1,4,3 respectively.
PROBLEM #2 (IDE-Reset):
When ATA device is used, the warm reset appears to hang the board, and the board has to be power-cycled.
PROBLEM #3 (ISA-DMA):
In the users manual revision 1.01, dated 6/9/1999, Board revision Level X2, Errata Revision Level B, shows that "The Winbond PCIRST signal conflicts with the PCIRST signal from the reset controller"; the reason being ISA-DMA does not seem to work. This problem will be fixed X3 revision of the board.
PROBLEM #4 (L2 CACHE):
In the PowerPC Evaluation System Users Manual Rev 4.01 dated 05/19/00, Board revision Level X2, Altimus Errata Revision Level A, says that Problem: "If MPC750/MPC755 CPU's are installed and MCM69p737 SRAM's are installed, pin B6(SE3) is undriven" "If MPC7400 CPU's is used, or if MCM69p737 SRAM's are used, then pin B6 is either driven (address A17) or is ignored by SRAM" Impact: "L2 cache may not operate or may not be reliable" Work-Around: "Add a pulldown to LA17" OR "Use late-write devices (69R737) that ignore pin B6(SE3) "
PROBLEM #5 (L3 CACHE on PPMC7450):
The Product page on the Motorola web site and the Valis documentation states that 2 MB of L3 cache is present. Actually only 1 MB of L3 Cache is present.
Impact: "If the L3 Cache is initialized with the L3 Cache size set to 2 MB, the system crashes." Work-Around: "Make sure that the L3 Cache Size is set to 1 MB when initializing the L3 Cache."
SW1 PPMC-7400 X2 / PPMC-750 / PPMC-755 / PPMC-7400 X3 / PPMC-7410 X3 1 ON 2 ON 3 ON 4 OFF 5 ON 6 ON 7 ON 8 OFF MPC75x/74xx PLL : 4X 133 266 333 400 MPC107 PLL
PCI=33 , BUS = 100
SW1 PPMC-7450 X1 PPMC7450 X2 Refer to the Sandpoint X3 Valis Documentation. MPC7450 (PPMC7450-X1) PLL
6X 400 500 600 800
MPC107 PLL
PCI=33 , BUS = 100
MPC7450 (PPMC7450-X2) PLL
8X 533 666 800
MPC107 PLL
PCI=33 , BUS = 100
MPC744x PLL : 6X 400 500 600 800 MPC107 PLL
PCI=33 , BUS = 100
SW1/SW2 PPMC-7455 X1/X2 Refer to the Sandpoint 111 Documentation. Note: As of this beta release for Tornado 2.2 the documentation is not available for the Switch settings. The BSP was tested with the settings that came preset. Update this section before RTM. SW1
1 2 3 4 5 6 7 8
ON OFF OFF ON ON ON ON OFF SW2
1 2 3 4 5 6 7 8
ON OFF ON OFF ON ON OFF OFF
lf3 lf3 lf3 lf3 l l l l . SW2
PPMC-7400 X2 / PPMC-755 / PPMC750
======================================= SYSRST
COP Resets only PrMC
PCI66MHZ
33 MHz Only
TRIGSEL
Trigger In
PROGSEL
RCS1 on Local ROM
AGENT
Free Agent
PrMCTYPE : MOTSPS PrPMC MAPSEL
Map B / CHRP
ROMLOC
RCS0 on PCI
SW2
PPMC-7400 X3 / PPMC-7410 X3 / PPMC-7450 X1/X2 / PPMC-744x X2
SYSRST
COP Resets only PrMC
M66EN
33 MHz Only
ROMSEL
Standard Flash Selected
PROGSEL
Local Flash is Bootable
AGENT
Free Agent
PMCTYPE
MOTSPS PrPMC
MAPSEL
Map B / CHRP
ROMLOC
RCS0 on PCI
The diagram below shows jumpers relevant to VxWorks configuration.
C C O O M PARA MOU KEY M 2 LLEL SE BORD 1 _____________________________________________________________________ | ________ | || || || || | | | s3|.____||_| |___||_____||___||___||___| | | ________ | | s4|_||____.| | | ___________________________ | | _ _ _ _ | | | | |p||p||p||p| | | | | |c||c||c||c| | | | | ______ |i||i||i||i| | P P M C | | |s6|.__||_| |s||s|| || | | | | | |l||l||s||s| | 8240 or 755 or 750 | | | |o||o||l||l| | 7400 or 7410 | | | |t||t||o||o| | | | | |3||4||t||t| | | | | |_||_|| || | |__________________________| | | |1||2| ___ | | | || | J J J | | | | | | || | ____ 3 3 3 | | | | |1 _ 2 ____ | || | | U6 | 0 2 1 | | | | | | | s5|___.| |_||_| | ROM| |_|_| | | | | |____| __ | | | |M R P | | | | | |I E O | | | | | |S S W | | | | | |C E E _ _ _________ | | | | | | _T R_ |J||J| |IDE 2 | | | | | | | |s2| |s1| |3||3| |_________| |__| | | |_| |__| |__| |3||4| __________ __________ | | ____B____ |_||_| |IDE 1 | |FLOPPY | | | |_________| 1|__________| 1|__________| | |_____________________________________________________________________| S3, S4 Mode Switches PPMC- Processor card B- Battery Connector Symbols (||) in Switches indicates default mode U6- Rom Socket
Tornado User's Guide: Getting Started, VxWorks Programmer's Guide: Configuration, VxWorks Programmer's Guide: Architecture Appendix
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Sandpoint User's Manual and Hardware Design Manual http://www.mot.com/SPS/PowerPC/teksupport/refdesigns/sandpoint.html MPC8240 Integrated Processor User's Manual MPC755 Processor User Manual MPC750 Processor User Manual MPC7400 Processor User Manual MPC7410 Processor User Manual SPS BSP user manual MPC107 PCI Bridge/Memory Controller User's Manual Addendum to MPC107 PCI Bridge/Memory Controller UserĘs Manual MPC107 Revision 4.0 Supplement and User's Manual Errata Winbond W83C553F SYSTEM I/O CONTROLLER WITH PCI ARBITER User Manual National Semiconductor PC87308VUL SuperIO User's Manual DEC 2114X Ethernet Controller User's Manual Intel 82557 Ethernet Controller User's Manual AMD 97X PCFAST Ethernet Controller User's Manual Am29F040B 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory Manual. PCI Local Bus Specification Revision 2.1 PowerPC Embedded Application Binary Interface 32-Bit Implementation Altimus X2 Release V1.1 Schematics