VxWorks BSP Reference : prpmc600
sysLib [prpmc600] - Motorola PrPMC600 board series system-dependent library
pciConfigLibInit( ) - initialize the configuration access-method and addresses
pciFindDevice( ) - find the nth device with the given device & vendor ID
pciFindClass( ) - find the nth occurence of a device by PCI class code.
pciDevConfig( ) - configure a device on a PCI bus
pciConfigBdfPack( ) - pack parameters for the Configuration Address Register
pciConfigExtCapFind( ) - find extended capability in ECP linked list
pciConfigInByte( ) - read one byte from the PCI configuration space
pciConfigInWord( ) - read one word from the PCI configuration space
pciConfigInLong( ) - read one longword from the PCI configuration space
pciConfigOutByte( ) - write one byte to the PCI configuration space
pciConfigOutWord( ) - write one 16-bit word to the PCI configuration space
pciConfigOutLong( ) - write one longword to the PCI configuration space
pciConfigModifyLong( ) - Perform a masked longword register update
pciConfigModifyWord( ) - Perform a masked longword register update
pciConfigModifyByte( ) - Perform a masked longword register update
pciSpecialCycle( ) - generate a special cycle with a message
pciConfigForeachFunc( ) - check condition on specified bus
pciConfigReset( ) - disable cards for warm boot
sysSerialHwInit( ) - initialize the BSP serial devices to a quiescent state
sysSerialHwInit2( ) - connect BSP serial device interrupts
sysSerialChanGet( ) - get the SIO_CHAN device associated with a serial channel
sysSerialReset( ) - reset all serial devices to a quiescent state
sysNvRamGet( ) - get the contents of non-volatile RAM
sysNvRamSet( ) - write to non-volatile RAM
sysReportVpdError( ) - routine to report errors in vpd data.
sysGetBusSpd( ) - routine to get the speed of the 60x processor bus
sysGetPciSpd( ) - routine to get the speed of the PCI bus
sysGetMpuSpd( ) - routine to get the speed of the 60x processor bus
sysVpdInit( ) - initialize the board vital product data structures.
sysClkConnect( ) - connect a routine to the system clock interrupt
sysClkEnable( ) - turn on system clock interrupts
sysClkDisable( ) - turn off system clock interrupts
sysClkRateGet( ) - get the system clock rate
sysClkRateSet( ) - set the system clock rate
sysNetHwInit( ) - initialize the network interface
sysNetHwInit2( ) - initialize additional features of the network interface
sysLanIntEnable( ) - enable the LAN interrupt
sysLanIntDisable( ) - disable the LAN interrupt
sysFei82557EndLoad( ) - load fei82557 (fei) device.
sys557PciInit( ) - prepare LAN adapter for 82557 initialization
sys557Init( ) - prepare LAN adapter for 82557 initialization
sys557eepromRead( ) - read a word from the 82557 EEPROM
sys557Show( ) - shows 82557 configuration
sysEpicInit( ) - initialize the EPIC
sysEpicIntHandler( ) - handle an interrupt received at the Epic
sysAuxClkInit( ) - mpc8240 aux. clock initialization routine
sysAuxClkConnect( ) - connect a routine to the auxiliary clock interrupt
sysAuxClkDisable( ) - turn off auxiliary clock interrupts
sysAuxClkEnable( ) - turn on auxiliary clock interrupts
sysAuxClkRateGet( ) - get the auxiliary clock rate
sysAuxClkRateSet( ) - set the auxiliary clock rate
pciAutoConfigLibInit( ) - initialize PCI autoconfig library.
pciAutoCfg( ) - Automatically configure all nonexcluded PCI headers.
pciAutoCfgCtl( ) - set or get pciAutoConfigLib options.
pciAutoDevReset( ) - Quiesce a PCI device and reset all writeable status bits.
pciAutoBusNumberSet( ) - Set the primary, secondary, and subordinate bus number.
pciAutoFuncDisable( ) - Disable a specific PCI function.
pciAutoFuncEnable( ) - Perform final configuration and enable a function.
pciAutoGetNextClass( ) - find the next device of specific type from probe list.
pciAutoRegConfig( ) - Assign PCI space to a single PCI base address register.
pciAutoAddrAlign( ) - Align a PCI address and check boundary conditions.
pciAutoConfig( ) - Automatically configure all nonexcluded PCI headers. Obsolete.
sysPciAutoConfig( ) - PCI autoConfig support routine
sysDec2155xInit( ) - initialize registers of the Dec2155x (Drawbridge) chip
sysDec2155xAdrsGet( ) - capture and save the base address of the dec2155x csr
sysDec2155xInit2( ) - perform phase 2 Dec2155x initialization
sysDec2155xIntClear( ) - clear a Dec2155x internal interrupt
sysDec2155xBusIntGen( ) - generate an out-bound cPCI bus interrupt
sysDec2155xIntDisable( ) - disable a Dec2155x internal interrupt
sysDec2155xIntEnable( ) - Enable a Dec2155x internal interrupt
sysDec2155xErrClr( ) - Dec2155x Error Clear routine
sysDec2155xIntr( ) - Dec2155x (Drawbridge) PCI-to-PCI interrupt handler
sysDec2155xChkEnables( ) - check the originating and target bus enables
sysPciConfig21554InLong( ) - Perform Dec21554 long input configuration access
sysModel( ) - return the model name of the CPU board
sysBspRev( ) - return the BSP version and revision number
sysDecDelay( ) - decrementer delay
sysHwInit( ) - initialize the system hardware
sysPhysMemTop( ) - get the address of the top of physical memory
sysMemTop( ) - get the address of the top of VxWorks memory
sysToMonitor( ) - transfer control to the ROM monitor
sysHwInit2( ) - initialize additional system hardware
sysProcNumGet( ) - get the processor number
sysProcNumSet( ) - set the processor number
sysLocalToBusAdrs( ) - convert a local CPU address to a PCI bus address
sysBusToLocalAdrs( ) - convert a PCI bus address to a local CPU address
sysBusTas( ) - test and set a location across the bus
sysBusTasClear( ) - clear a location set by sysBusTas( )
sysNvRead( ) - read one byte from NVRAM
sysNvWrite( ) - write one byte to NVRAM
sysCpuCheck( ) - confirm the CPU type
sysProbeErrClr( ) - clear errors associated with probing an address on a bus.
sysPciProbe( ) - probe a PCI bus address
sysBusProbe( ) - probe a bus address based on bus type.
sysUsDelay( ) - delay at least the specified amount of time (in microseconds)
sysDebugMsg( ) - print a debug string to the console in polled mode.
sysPciInsertLong( ) - Insert field into PCI data long
sysPciInsertWord( ) - Insert field into PCI data word
sysPciInsertByte( ) - Insert field into PCI data byte
sysPciOutByteConfirm( ) - Byte out to PCI memory space and flush buffers.
sysPciOutWordConfirm( ) - Word out to PCI memory space and flush buffers.
sysPciOutLongConfirm( ) - Long word out to PCI memory space and flush buffers.
sysAtuInit( ) - initialize ATU
sysIntDisable( ) - disable a bus interrupt level (vector)
sysIntEnable( ) - enable a bus interrupt level (vector)
sysBusIntAck( ) - acknowledge a bus interrupt
sysBusIntGen( ) - generate a bus interrupt
sysMailboxConnect( ) - connect a routine to the in-bound mailbox interrupt
sysMailboxEnable( ) - enable the in-bound mailbox interrupt
sysMailboxDisable( ) - disable the in-bound mailbox interrupt
This library provides board-specific routines. The chip drivers included are:
i8250Sio.c - Intel 8250 UART driver
ppcDecTimer.c - PowerPC decrementer timer library (system clock)
byteNvRam.c - byte-oriented generic non-volatile RAM library
pciConfigLib.c - PCI configuration library
dec2155xCpci.c - Dec/Intel non-transparent PCI-to-PCI bridge library
mpc8240Epic.c - Mpc8240 Interrupt Controller
sysMotI2c.c - Mpc8240 I2C interface driver
sysLib.h
VxWorks Programmer's Guide: Configuration
pciConfigLibInit( ) - initialize the configuration access-method and addresses
STATUS pciConfigLibInit ( int mechanism, /* configuration mechanism: 0, 1, 2 */ ULONG addr0, /* config-addr-reg / CSE-reg */ ULONG addr1, /* config-data-reg / Forward-reg */ ULONG addr2 /* none / Base-address */ )
This routine initializes the configuration access-method and addresses.
Configuration mechanism one utilizes two 32-bit IO ports located at addresses 0x0cf8 and 0x0cfc. These two ports are:
- P"
- 32-bit configuration address port, at 0x0cf8
- P"
- 32-bit configuration data port, at 0x0cfc
Accessing a PCI function's configuration port is two step process.
- P"
- Write the bus number, physical device number, function number and register number to the configuration address port.
- P"
- Perform an IO read from or an write to the configuration data port.
Configuration mechanism two uses following two single-byte IO ports.
- P"
- Configuration space enable, or CSE, register, at 0x0cf8
- P"
- Forward register, at 0x0cfa
To generate a PCI configuration transaction, the following actions are performed.
* Configuration mechanism zero is for non-PC/PowerPC environments where an area of address space produces PCI configuration transactions. No support for special cycles is included.
- -
- Write the target bus number into the forward register.
- -
- Write a one byte value to the CSE register at 0x0cf8. The bit pattern written to this register has three effects: disables the generation of special cycles; enables the generation of configuration transactions; specifies the target PCI functional device.
- -
- Perform a one, two or four byte IO read or write transaction within the IO range 0xc000 through 0xcfff.
OK, or ERROR if a mechanism is not 0, 1, or 2.
pciFindDevice( ) - find the nth device with the given device & vendor ID
STATUS pciFindDevice ( int vendorId, /* vendor ID */ int deviceId, /* device ID */ int index, /* desired instance of device */ int * pBusNo, /* bus number */ int * pDeviceNo, /* device number */ int * pFuncNo /* function number */ )
This routine finds the nth device with the given device & vendor ID.
OK, or ERROR if the deviceId and vendorId didn't match.
pciFindClass( ) - find the nth occurence of a device by PCI class code.
STATUS pciFindClass ( int classCode, /* 24-bit class code */ int index, /* desired instance of device */ int * pBusNo, /* bus number */ int * pDeviceNo, /* device number */ int * pFuncNo /* function number */ )
This routine finds the nth device with the given 24-bit PCI class code (class subclass prog_if).
The classcode arg of must be carfully constructed from class and sub-class macros.
Example : To find an ethernet class device, construct the classcode arg as follows:
((PCI_CLASS_NETWORK_CTLR << 16 | PCI_SUBCLASS_NET_ETHERNET << 8))
OK, or ERROR if the class didn't match.
pciDevConfig( ) - configure a device on a PCI bus
STATUS pciDevConfig ( int pciBusNo, /* PCI bus number */ int pciDevNo, /* PCI device number */ int pciFuncNo, /* PCI function number */ UINT32 devIoBaseAdrs, /* device IO base address */ UINT32 devMemBaseAdrs, /* device memory base address */ UINT32 command /* command to issue */ )
This routine configures a device that is on a Peripheral Component Interconnect (PCI) bus by writing to the configuration header of the selected device.
It first disables the device by clearing the command register in the configuration header. It then sets the I/O and/or memory space base address registers, the latency timer value and the cache line size. Finally, it re-enables the device by loading the command register with the specified command.
This routine is designed for Type 0 PCI Configuration Headers ONLY. It is NOT usable for configuring, for example, a PCI-to-PCI bridge.
OK always.
pciConfigBdfPack( ) - pack parameters for the Configuration Address Register
int pciConfigBdfPack ( int busNo, /* bus number */ int deviceNo, /* device number */ int funcNo /* function number */ )
This routine packs three parameters into one integer for accessing the Configuration Address Register
packed integer encoded version of bus, device, and function numbers.
pciConfigExtCapFind( ) - find extended capability in ECP linked list
STATUS pciConfigExtCapFind ( UINT8 extCapFindId, /* Extended capabilities ID to search for */ int bus, /* PCI bus number */ int device, /* PCI device number */ int function, /* PCI function number */ UINT8 * pOffset /* returned config space offset */ )
This routine searches for an extended capability in the linked list of capabilities in config space. If found, the offset of the first byte of the capability of interest in config space is returned via pOffset.
OK if Extended Capability found, ERROR otherwise
pciConfigInByte( ) - read one byte from the PCI configuration space
STATUS pciConfigInByte ( int busNo, /* bus number */ int deviceNo, /* device number */ int funcNo, /* function number */ int offset, /* offset into the configuration space */ UINT8 * pData /* data read from the offset */ )
This routine reads one byte from the PCI configuration space
OK, or ERROR if this library is not initialized
pciConfigInWord( ) - read one word from the PCI configuration space
STATUS pciConfigInWord ( int busNo, /* bus number */ int deviceNo, /* device number */ int funcNo, /* function number */ int offset, /* offset into the configuration space */ UINT16 * pData /* data read from the offset */ )
This routine reads one word from the PCI configuration space
OK, or ERROR if this library is not initialized
pciConfigInLong( ) - read one longword from the PCI configuration space
STATUS pciConfigInLong ( int busNo, /* bus number */ int deviceNo, /* device number */ int funcNo, /* function number */ int offset, /* offset into the configuration space */ UINT32 * pData /* data read from the offset */ )
This routine reads one longword from the PCI configuration space
OK, or ERROR if this library is not initialized
pciConfigOutByte( ) - write one byte to the PCI configuration space
STATUS pciConfigOutByte ( int busNo, /* bus number */ int deviceNo, /* device number */ int funcNo, /* function number */ int offset, /* offset into the configuration space */ UINT8 data /* data written to the offset */ )
This routine writes one byte to the PCI configuration space.
OK, or ERROR if this library is not initialized
pciConfigOutWord( ) - write one 16-bit word to the PCI configuration space
STATUS pciConfigOutWord ( int busNo, /* bus number */ int deviceNo, /* device number */ int funcNo, /* function number */ int offset, /* offset into the configuration space */ UINT16 data /* data written to the offset */ )
This routine writes one 16-bit word to the PCI configuration space.
OK, or ERROR if this library is not initialized
pciConfigOutLong( ) - write one longword to the PCI configuration space
STATUS pciConfigOutLong ( int busNo, /* bus number */ int deviceNo, /* device number */ int funcNo, /* function number */ int offset, /* offset into the configuration space */ UINT32 data /* data written to the offset */ )
This routine writes one longword to the PCI configuration space.
OK, or ERROR if this library is not initialized
pciConfigModifyLong( ) - Perform a masked longword register update
STATUS pciConfigModifyLong ( int busNo, /* bus number */ int deviceNo, /* device number */ int funcNo, /* function number */ int offset, /* offset into the configuration space */ UINT32 bitMask, /* Mask which defines field to alter */ UINT32 data /* data written to the offset */ )
This function writes a field into a PCI configuration header without altering any bits not present in the field. It does this by first doing a PCI configuration read (into a temporary location) of the PCI configuration header word which contains the field to be altered. It then alters the bits in the temporary location to match the desired value of the field. It then writes back the temporary location with a configuration write. All configuration accesses are long and the field to alter is specified by the "1" bits in the bitMask parameter.
Be careful to using pciConfigModifyLong for updating the Command and status register. The status bits must be written back as zeroes, else they will be cleared. Proper use involves including the status bits in the mask value, but setting their value to zero in the data value.
The following example will set the PCI_CMD_IO_ENABLE bit without clearing any status bits. The macro PCI_CMD_MASK includes all the status bits as part of the mask. The fact that PCI_CMD_MASTER doesn't include these bits, causes them to be written back as zeroes, therefore they aren't cleared.
pciConfigModifyLong (b,d,f,PCI_CFG_COMMAND, (PCI_CMD_MASK | PCI_CMD_IO_ENABLE), PCI_CMD_IO_ENABLE);Use of explicit longword read and write operations for dealing with any register containing "write 1 to clear" bits is sound policy.
OK if operation succeeds, ERROR if operation fails.
pciConfigModifyWord( ) - Perform a masked longword register update
STATUS pciConfigModifyWord ( int busNo, /* bus number */ int deviceNo, /* device number */ int funcNo, /* function number */ int offset, /* offset into the configuration space */ UINT16 bitMask, /* Mask which defines field to alter */ UINT16 data /* data written to the offset */ )
This function writes a field into a PCI configuration header without altering any bits not present in the field. It does this by first doing a PCI configuration read (into a temporary location) of the PCI configuration header word which contains the field to be altered. It then alters the bits in the temporary location to match the desired value of the field. It then writes back the temporary location with a configuration write. All configuration accesses are long and the field to alter is specified by the "1" bits in the bitMask parameter.
Do not use this routine to modify any register that contains write 1 to clear type of status bits in the same longword. This specifically applies to the command register. Modify byte operations could potentially be implemented as longword operations with bit shifting and masking. This could have the effect of clearing status bits in registers that aren't being updated. Use pciConfigInLong and pciConfigOutLong, or pciModifyLong, to read and update the entire longword.
OK if operation succeeds. ERROR if operation fails.
pciConfigModifyByte( ) - Perform a masked longword register update
STATUS pciConfigModifyByte ( int busNo, /* bus number */ int deviceNo, /* device number */ int funcNo, /* function number */ int offset, /* offset into the configuration space */ UINT8 bitMask, /* Mask which defines field to alter */ UINT8 data /* data written to the offset */ )
This function writes a field into a PCI configuration header without altering any bits not present in the field. It does this by first doing a PCI configuration read (into a temporary location) of the PCI configuration header word which contains the field to be altered. It then alters the bits in the temporary location to match the desired value of the field. It then writes back the temporary location with a configuration write. All configuration accesses are long and the field to alter is specified by the "1" bits in the bitMask parameter.
Do not use this routine to modify any register that contains write 1 to clear type of status bits in the same longword. This specifically applies to the command register. Modify byte operations could potentially be implemented as longword operations with bit shifting and masking. This could have the effect of clearing status bits in registers that aren't being updated. Use pciConfigInLong and pciConfigOutLong, or pciModifyLong, to read and update the entire longword.
OK if operation succeeds, ERROR if operation fails.
pciSpecialCycle( ) - generate a special cycle with a message
STATUS pciSpecialCycle ( int busNo, /* bus number */ UINT32 message /* data driven onto AD[31:0] */ )
This routine generates a special cycle with a message.
OK, or ERROR if this library is not initialized
pciConfigForeachFunc( ) - check condition on specified bus
STATUS pciConfigForeachFunc ( UINT8 bus, /* bus to start on */ BOOL recurse, /* if TRUE, do subordinate busses */ PCI_FOREACH_FUNC funcCheckRtn, /* routine to call for each PCI func */ void * pArg /* argument to funcCheckRtn */ )
pciConfigForeachFunc( ) discovers the PCI functions present on the bus and calls a specified C-function for each one. If the function returns ERROR, further processing stops.
pciConfigForeachFunc( ) does not affect any HOST<->PCI bridge on the system.
not set
OK normally, or ERROR if funcCheckRtn( ) doesn't return OK.
pciConfigReset( ) - disable cards for warm boot
STATUS pciConfigReset ( int startType /* for reboot hook, ignored */ )
pciConfigReset( ) goes through the list of PCI functions at the top-level bus and disables them, preventing them from writing to memory while the system is trying to reboot.
Not set
OK, always
sysSerialHwInit( ) - initialize the BSP serial devices to a quiescent state
void sysSerialHwInit (void)
This routine initializes the BSP serial device descriptors and puts the devices in a quiescent state. It is called from sysHwInit( ) with interrupts locked. Polled mode serial operations are possible, but not interrupt mode operations which are enabled by sysSerialHwInit2( ).
N/A
sysLib, sysHwInit( ), sysSerialHwInit2( )
sysSerialHwInit2( ) - connect BSP serial device interrupts
void sysSerialHwInit2 (void)
This routine connects the BSP serial device interrupts. It is called from sysHwInit2( ).
Serial device interrupts cannot be connected in sysSerialHwInit( ) because the kernel memory allocator is not initialized at that point, and intConnect( ) calls malloc( ).
N/A
sysLib, sysHwInit2( )
sysSerialChanGet( ) - get the SIO_CHAN device associated with a serial channel
SIO_CHAN * sysSerialChanGet ( int channel /* serial channel */ )
This routine returns a pointer to the SIO_CHAN device associated with a specified serial channel. It is called by usrRoot( ) to obtain pointers when creating the system serial devices, /tyCo/x. It is also used by the WDB agent to locate its serial channel.
A pointer to the SIO_CHAN structure for the channel, or ERROR if the channel is invalid.
sysSerialReset( ) - reset all serial devices to a quiescent state
void sysSerialReset (void)
This routine resets all serial devices to a quiescent state. It is called by sysToMonitor( ).
N/A
sysLib, sysToMonitor( )
sysNvRamGet( ) - get the contents of non-volatile RAM
STATUS sysNvRamGet ( char * string, /* where to copy non-volatile RAM */ int strLen, /* maximum number of bytes to copy */ int offset /* byte offset into non-volatile RAM */ )
This routine copies the contents of non-volatile memory into a specified string. The string is terminated with an EOS.
OK, or ERROR if access is outside the non-volatile RAM range.
sysLib, sysNvRamSet( )
sysNvRamSet( ) - write to non-volatile RAM
STATUS sysNvRamSet ( char * string, /* string to be copied into non-volatile RAM */ int strLen, /* maximum number of bytes to copy */ int offset /* byte offset into non-volatile RAM */ )
This routine copies a specified string into non-volatile RAM.
OK, or ERROR if access is outside the non-volatile RAM range.
sysLib, sysNvRamGet( )
sysReportVpdError( ) - routine to report errors in vpd data.
void sysReportVpdError ( char * str /* message to display */ )
This routine prints an error message at the system console and optionally returns to the boot rom.
N/A
sysGetBusSpd( ) - routine to get the speed of the 60x processor bus
UINT sysGetBusSpd (void)
This routine returns the speed (in Hz) of the 60x system bus.
The bus speed (inHz).
sysGetPciSpd( ) - routine to get the speed of the PCI bus
UINT sysGetPciSpd (void)
This routine returns the speed (in Hz) of the PCI bus.
The bus speed (inHz).
sysGetMpuSpd( ) - routine to get the speed of the 60x processor bus
UINT sysGetMpuSpd (void)
This routine returns the speed (in Hz) of the 60x system bus.
The bus speed (inHz).
sysVpdInit( ) - initialize the board vital product data structures.
STATUS sysVpdInit (void)
This routine reads the VPD and extracts the commonly used data.
OK, if successful or ERROR if unsuccessful.
sysLib, N/A( )
sysClkConnect( ) - connect a routine to the system clock interrupt
STATUS sysClkConnect ( FUNCPTR routine, /* routine to connect */ int arg /* argument for the routine */ )
This routine specifies the interrupt service routine to be called at each clock interrupt. Normally, it is called from usrRoot( ) in usrConfig.c to connect usrClock( ) to the system clock interrupt.
OK, or ERROR if the routine cannot be connected to the interrupt.
sysLib, intConnect( ), usrClock( ), sysClkEnable( )
sysClkEnable( ) - turn on system clock interrupts
void sysClkEnable (void)
This routine enables system clock interrupts.
N/A
sysLib, sysClkConnect( ), sysClkDisable( ), sysClkRateSet( )
sysClkDisable( ) - turn off system clock interrupts
void sysClkDisable (void)
This routine disables system clock interrupts.
N/A
sysLib, sysClkEnable( )
sysClkRateGet( ) - get the system clock rate
int sysClkRateGet (void)
This routine returns the system clock rate.
The number of ticks per second of the system clock.
sysLib, sysClkEnable( ), sysClkRateSet( )
sysClkRateSet( ) - set the system clock rate
STATUS sysClkRateSet ( int ticksPerSecond /* number of clock interrupts per second */ )
This routine sets the interrupt rate of the system clock. It is called by usrRoot( ) in usrConfig.c.
OK, or ERROR if the tick rate is invalid or the timer cannot be set.
sysLib, sysClkEnable( ), sysClkRateGet( )
sysNetHwInit( ) - initialize the network interface
void sysNetHwInit (void)
This routine initializes the network hardware to a quiescent state. It does not connect interrupts.
Only polled mode operation is possible after calling this routine. Interrupt mode operation is possible after the memory system has been initialized and sysNetHwInit2( ) has been called.
sysNetHwInit2( ) - initialize additional features of the network interface
void sysNetHwInit2 (void)
This routine completes initialization needed for interrupt mode operation of the network device drivers. Interrupt handlers can be connected. Interrupt or DMA operations can begin.
sysLanIntEnable( ) - enable the LAN interrupt
STATUS sysLanIntEnable ( int intLevel /* interrupt level to enable */ )
This routine enables interrupts at a specified level
OK, or ERROR if network support not included.
sysLanIntDisable( ) - disable the LAN interrupt
STATUS sysLanIntDisable ( int intLevel /* interrupt level to enable */ )
This routine has been modified and is temporarily a stub. Changes to the WRS 21x40End driver are required to switch from a dedicated interrupt line for the Ethernet chip to the bussed PCI interrupt structure used by the PPMC750. This change is also required to support Ethernet chips resident on PMC sites. WRS has assigned SPR #27879 to track the 21x40End driver change.
return of intDisable, or ERROR if network support not included.
sysFei82557EndLoad( ) - load fei82557 (fei) device.
END_OBJ * sysFei82557EndLoad ( char * pParamStr, /* ptr to initialization parameter string */ void * unused /* unused optional argument */ )
This routine loads the fei device with initial parameters.
pointer to END object or NULL.
sys557PciInit( ) - prepare LAN adapter for 82557 initialization
void sys557PciInit (void)
This routine find out the PCI device, and map its memory and IO address. It must be done prior to initializing the 82557, sys557Init( ). Also must be done prior to MMU initialization, usrMmuInit( ).
N/A
sys557Init( ) - prepare LAN adapter for 82557 initialization
STATUS sys557Init ( int unit, /* unit number */ FEI_BOARD_INFO * pBoard /* board information for the end driver */ )
This routine is expected to perform any adapter-specific or target-specific initialization that must be done prior to initializing the 82557.
The 82557 driver calls this routine from the driver attach routine before any other routines in this library.
This routine returns the interrupt level the pIntLvl parameter.
OK or ERROR if the adapter could not be prepared for initialization.
sys557eepromRead( ) - read a word from the 82557 EEPROM
UINT16 sys557eepromRead ( int unit, /* unit number */ int location /* address of word to be read */ )
the EEPROM data word read in.
sys557Show( ) - shows 82557 configuration
void sys557Show ( int unit /* unit number */ )
this routine shows (Intel Pro Express 100) configuration
N/A
sysEpicInit( ) - initialize the EPIC
STATUS sysEpicInit (void)
This function initializes the Embedded Programmable Interrupt Controller (EPIC) contained in the Mpc8240 chip.
It first initializes the system vector table, connects the EPIC interrupt handler to the PPC external interrupt and attaches the local EPIC routines for interrupt connecting, enabling and disabling to the corresponding system routine pointers.
It then initializes the EPIC registers, clears any pending EPIC interrupts, and enables interrupt handling by the EPIC.
OK always
sysEpicIntHandler( ) - handle an interrupt received at the Epic
void sysEpicIntHandler (void)
This routine will process interrupts received from PCI or ISA devices as these interrupts arrive via the EPIC. This routine supports EPIC interrupt nesting.
N/A
sysAuxClkInit( ) - mpc8240 aux. clock initialization routine
STATUS sysAuxClkInit (void)
This routine should be called before calling any other routine in this module.
OK, or ERROR.
sysAuxClkConnect( ) - connect a routine to the auxiliary clock interrupt
STATUS sysAuxClkConnect ( FUNCPTR routine, /* routine called at each aux clock interrupt */ int arg /* argument with which to call routine */ )
This routine specifies the interrupt service routine to be called at each auxiliary clock interrupt.
OK, or ERROR if the routine cannot be connected to the interrupt.
sysLib, intConnect( ), sysAuxClkEnable( )
sysAuxClkDisable( ) - turn off auxiliary clock interrupts
void sysAuxClkDisable (void)
This routine disables auxiliary clock interrupts.
N/A
sysAuxClkEnable( ) - turn on auxiliary clock interrupts
void sysAuxClkEnable (void)
This routine enables auxiliary clock interrupts.
N/A
sysAuxClkRateGet( ) - get the auxiliary clock rate
int sysAuxClkRateGet (void)
This routine returns the interrupt rate of the auxiliary clock.
The number of ticks per second of the auxiliary clock.
sysLib, sysAuxClkEnable( ), sysAuxClkRateSet( )
sysAuxClkRateSet( ) - set the auxiliary clock rate
STATUS sysAuxClkRateSet ( int ticksPerSecond /* number of clock interrupts per second */ )
This routine sets the interrupt rate of the auxiliary clock. It is not supported, since the auxiliary clock always runs at the same rate as the system clock.
OK or ERROR.
sysLib, sysAuxClkEnable( ), sysAuxClkRateGet( )
pciAutoConfigLibInit( ) - initialize PCI autoconfig library.
void * pciAutoConfigLibInit ( void * pArg /* reserved for future use */ )
pciAutoConfigLib initialization function.
not set
A cookie for use by subsequent pciAutoConfigLib function
calls.
pciAutoCfg( ) - Automatically configure all nonexcluded PCI headers.
STATUS pciAutoCfg ( void * pCookie /* cookie returned by pciAutoConfigLibInit() */ )
Top level function in the PCI configuration process.
pCookie = pciAutoConfigLibInit(NULL); pciAutoCfgCtl(pCookie, COMMAND, VALUE); ... pciAutoCfgCtl(pCookie, COMMAND, VALUE); pciAutoCfg(pCookie);For ease in converting from the old interface to the new one, a pciAutoCfgCtl( ) command PCI_PSYSTEM_STRUCT_COPY has been implemented. This can be used just like any other pciAutoCfgCtl( ) command, and it will initialize all the values in pSystem. If used, it should be the first call to pciAutoCfgCtl( ).For a description of the COMMANDs and VALUEs to pciAutoCfgCtl( ), see the pciAutoCfgCtl( ) documentation.
For all nonexcluded PCI functions on all PCI bridges, this routine will automatically configure the PCI configuration headers for PCI devices and subbridges. The fields that are programmed are:
1. Status register. 2. Command Register. 3. Latency timer. 4. Cache Line size. 5. Memory and/or I/O base address and limit registers. 6. Primary, secondary, subordinate bus number (for PCI-PCI bridges). 7. Expansion ROM disable. 8. Interrupt Line.
Probe PCI config space and create a list of available PCI functions. Call device exclusion function, if registered, to exclude/include device. Disable all devices before we initialize any. Allocate and assign PCI space to each device. Calculate and set interrupt line value. Initialize and enable each device.
N/A.
pciAutoCfgCtl( ) - set or get pciAutoConfigLib options.
STATUS pciAutoCfgCtl ( void * pCookie, /* system configuration information */ int cmd, /* command word */ void * pArg /* argument for the cmd */ )
pciAutoCfgCtl( ) can be considered analogous to ioctl( ) calls: the call takes arguments of (1) a pCookie, returned by pciAutoConfigLibInit( ). (2) A command, macros for which are defined in pciAutoConfigLib.h. And, (3) an argument, the type of which depends on the specific command, but will always fit in a pointer variable. Currently, only globally effective commands are implemented.
The commands available are:
- PCI_FBB_ENABLE - BOOL * pArg
- PCI_FBB_DISABLE - void
- PCI_FBB_UPDATE - BOOL * pArg
- PCI_FBB_STATUS_GET - BOOL * pArg
- Enable and disable the functions which check Fast Back To Back functionality. PCI_FBB_UPDATE is for use with dynamic/HA applications. It will first disable FBB on all functions, then enable FBB on all functions, if appropriate. In HA applications, it should be called any time a card is added or removed. The BOOL pointed to by pArg for PCI_FBB_ENABLE and PCI_FBB_UPDATE will be set to TRUE if all cards allow FBB functionality and FALSE if either any card does not allow FBB functionality or if FBB is disabled. The BOOL pointed to by pArg for PCI_FBB_STATUS_GET will be set to TRUE if PCI_FBB_ENABLE has been called and FBB is enabled, even if FBB is not activated on any card. It will be set to FALSE otherwise.
Note that in the current implementation, FBB will be enabled or disabled on the entire bus. If any device anywhere on the bus cannot support FBB, then it is not enabled, even if specific sub-busses could support it.
- PCI_MAX_LATENCY_FUNC_SET - FUNCPTR * pArg
- This routine will be called for each function present on the bus when discovery takes place. The routine must accept four arguments, specifying bus, device, function, and a user-supplied argument of type void *. See PCI_MAX_LATENCY_ARG_SET. The routine should return a UINT8 value, which will be put into the MAX_LAT field of the header structure. The user supplied routine must return a valid value each time it is called. There is no mechanism for any ERROR condition, but a default value can be returned in such a case. Default = NULL.
- PCI_MAX_LATENCY_ARG_SET - void * pArg
- When the routine specified in PCI_MAX_LATENCY_FUNC_SET is called, this will be passed to it as the fourth argument.
- PCI_MAX_LAT_ALL_SET - int pArg
- Specifies a constant max latency value for all cards, if no function has been specified with PCI_MAX_LATENCY_FUNC_SET..
- PCI_MAX_LAT_ALL_GET - UINT * pArg
- Retrieves the value of max latency for all cards, if no function has been specified with PCI_MAX_LATENCY_FUNC_SET. Otherwise, the integer pointed to by pArg is set to the value 0xffffffff.
- PCI_MSG_LOG_SET - FUNCPTR * pArg
- The argument specifies a routine will be called to print warning or error messages from pciAutoConfigLib if logMsg( ) has not been initialized at the time pciAutoConfigLib is used. The specified routine must accept arguments in the same format as logMsg( ), but it does not necessarily need to print the actual message. An example of this routine is presented below, which saves the message into a safe memory space and turns on an LED. This command is useful for BSPs which call pciAutoCfg( ) before message logging is enabled. Note that after logMsg( ) is configured, output will go to logMsg( ) even if this command has been called. Default = NULL.
/* sample PCI_MSG_LOG_SET function */ int pciLogMsg(char *fmt,int a1,int a2,int a3,int a4,int a5,int a6) { sysLedOn(4); return(sprintf(sysExcMsg,fmt,a1,a2,a3,a4,a5,a6)); }- PCI_MAX_BUS_GET - int * pArg
- During autoconfiguration, the library will maintain a counter with the highest numbered bus. This can be retrieved by
pciAutoCfgCtl(pCookie, PCI_MAX_BUS_GET, &maxBus)- PCI_CACHE_SIZE_SET - int pArg
- Sets the pci cache line size to the specified value. See CONFIGURATION SPACE PARAMETERS in the pciAutoConfigLib documentation for more details.
- PCI_CACHE_SIZE_GET - int * pArg
- Retrieves the value of the pci cache line size.
- PCI_AUTO_INT_ROUTE_SET - BOOL pArg
- Enables or disables automatic interrupt routing across bridges during the autoconfig process. See "INTERRUPT ROUTING ACROSS PCI-TO-PCI BRIDGES" in the pciAutoConfigLib documentation for more details.
- PCI_AUTO_INT_ROUTE_GET - BOOL * pArg
- Retrieves the status of automatic interrupt routing.
- PCI_MEM32_LOC_SET - UINT32 pArg
- Sets the base address of the PCI 32-bit memory space. Normally, this is given by the BSP constant PCI_MEM_ADRS.
- PCI_MEM32_SIZE_SET - UINT32 pArg
- Sets the maximum size to use for the PCI 32-bit memory space. Normally, this is given by the BSP constant PCI_MEM_SIZE.
- PCI_MEM32_SIZE_GET - UINT32 * pArg
- After autoconfiguration has been completed, this retrieves the actual amount of space which has been used for the PCI 32-bit memory space.
- PCI_MEMIO32_LOC_SET - UINT32 pArg
- Sets the base address of the PCI 32-bit non-prefetch memory space. Normally, this is given by the BSP constant PCI_MEMIO_ADRS.
- PCI_MEMIO32_SIZE_SET - UINT32 pArg
- Sets the maximum size to use for the PCI 32-bit non-prefetch memory space. Normally, this is given by the BSP constant PCI_MEMIO_SIZE.
- PCI_MEMIO32_SIZE_GET - UINT32 * pArg
- After autoconfiguration has been completed, this retrieves the actual amount of space which has been used for the PCI 32-bit non-prefetch memory space.
- PCI_IO32_LOC_SET - UINT32 pArg
- Sets the base address of the PCI 32-bit I/O space. Normally, this is given by the BSP constant PCI_IO_ADRS.
- PCI_IO32_SIZE_SET - UINT32 pArg
- Sets the maximum size to use for the PCI 32-bit I/O space. Normally, this is given by the BSP constant PCI_IO_SIZE.
- PCI_IO32_SIZE_GET - UINT32 * pArg
- After autoconfiguration has been completed, this retrieves the actual amount of space which has been used for the PCI 32-bit I/O space.
- PCI_IO16_LOC_SET - UINT32 pArg
- Sets the base address of the PCI 16-bit I/O space. Normally, this is given by the BSP constant PCI_ISA_IO_ADRS
- PCI_IO16_SIZE_SET - UINT32 pArg
- Sets the maximum size to use for the PCI 16-bit I/O space. Normally, this is given by the BSP constant PCI_ISA_IO_SIZE
- PCI_IO16_SIZE_GET - UINT32 * pArg
- After autoconfiguration has been completed, this retrieves the actual amount of space which has been used for the PCI 16-bit I/O space.
- PCI_INCLUDE_FUNC_SET - FUNCPTR * pArg
- The device inclusion routine is specified by assigning a function pointer with the PCI_INCLUDE_FUNC_SET pciAutoCfgCtl( ) command:
pciAutoCfgCtl(pSystem, PCI_INCLUDE_FUNC_SET,sysPciAutoconfigInclude);This optional user-supplied routine takes as input both the bus-device-function tuple, and a 32-bit quantity containing both the PCI vendorID and deviceID of the function. The function prototype for this function is shown below:STATUS sysPciAutoconfigInclude ( PCI_SYSTEM *pSys, PCI_LOC *pLoc, UINT devVend );This optional user-specified routine is called by PCI AutoConfig for each and every function encountered in the scan phase. The BSP developer may use any combination of the input data to ascertain whether a device is to be excluded from the autoconfig process. The exclusion routine then returns ERROR if a device is to be excluded, and OK if a device is to be included in the autoconfiguration process.Note that PCI-to-PCI Bridges may not be excluded, regardless of the value returned by the BSP device inclusion routine. The return value is ignored for PCI-to-PCI bridges.
The Bridge device will be always be configured with proper primary, secondary, and subordinate bus numbers in the device scanning phase and proper I/O and Memory aperture settings in the configuration phase of autoconfig regardless of the value returned by the BSP device inclusion routine.
- PCI_INT_ASSIGN_FUNC_SET - FUNCPTR * pArg
- The interrupt assignment routine is specified by assigning a function pointer with the PCI_INCLUDE_FUNC_SET pciAutoCfgCtl( ) command:
pciAutoCfgCtl(pCookie, PCI_INT_ASSIGN_FUNC_SET, sysPciAutoconfigIntrAssign);This optional user-specified routine takes as input both the bus-device-function tuple, and an 8-bit quantity containing the contents of the interrupt Pin register from the PCI configuration header of the device under consideration. The interrupt pin register specifies which of the four PCI Interrupt request lines available are connected. The function prototype for this function is shown below:UCHAR sysPciAutoconfigIntrAssign ( PCI_SYSTEM *pSys, PCI_LOC *pLoc, UCHAR pin );This routine may use any combination of these data to ascertain the interrupt level. This value is returned from the function, and will be programmed into the interrupt line register of the function's PCI configuration header. In this manner, device drivers may subsequently read this register in order to calculate the appropriate interrupt vector which to attach an interrupt service routine.
- PCI_BRIDGE_PRE_CONFIG_FUNC_SET - FUNCPTR * pArg
- The bridge pre-configuration pass initialization routine is provided so that the BSP Developer can initialize a bridge device prior to the configuration pass on the bus that the bridge implements. This routine is specified by calling pciAutoCfgCtl( ) with the PCI_BRIDGE_PRE_CONFIG_FUNC_SET command:
pciAutoCfgCtl(pCookie, PCI_BRIDGE_PRE_CONFIG_FUNC_SET, sysPciAutoconfigPreEnumBridgeInit);This optional user-specified routine takes as input both the bus-device-function tuple, and a 32-bit quantity containing both the PCI deviceID and vendorID of the device. The function prototype for this function is shown below:STATUS sysPciAutoconfigPreEnumBridgeInit ( PCI_SYSTEM *pSys, PCI_LOC *pLoc, UINT devVend );This routine may use any combination of these input data to ascertain any special initialization requirements of a particular type of bridge at a specified geographic location.
- PCI_BRIDGE_POST_CONFIG_FUNC_SET - FUNCPTR * pArg
- The bridge post-configuration pass initialization routine is provided so that the BSP Developer can initialize the bridge device after the bus that the bridge implements has been enumerated. This routine is specified by calling pciAutoCfgCtl( ) with the PCI_BRIDGE_POST_CONFIG_FUNC_SET command
pciAutoCfgCtl(pCookie, PCI_BRIDGE_POST_CONFIG_FUNC_SET, sysPciAutoconfigPostEnumBridgeInit);This optional user-specified routine takes as input both the bus-device-function tuple, and a 32-bit quantity containing both the PCI deviceID and vendorID of the device. The function prototype for this function is shown below:STATUS sysPciAutoconfigPostEnumBridgeInit ( PCI_SYSTEM *pSys, PCI_LOC *pLoc, UINT devVend );This routine may use any combination of these input data to ascertain any special initialization requirements of a particular type of bridge at a specified geographic location.
- PCI_ROLLCALL_FUNC_SET - FUNCPTR * pArg
- The specified routine will be configured as a roll call routine.
If a roll call routine has been configured, before any configuration is actually done, the roll call routine is called repeatedly until it returns TRUE. A return value of TRUE indicates that either (1) the specified number and type of devices named in the roll call list have been found during PCI bus enumeration or (2) the timeout has expired without finding all of the specified number and type of devices. In either case, it is assumed that all of the PCI devices which are going to appear on the busses have appeared and we can proceed with PCI bus configuration.
- PCI_TEMP_SPACE_SET - char * pArg
- This command is not currently implemented. It allows the user to set aside memory for use during pciAutoConfigLib execution, e.g. memory set aside using USER_RESERVED_MEM. After PCI configuration has been completed, the memory can be added to the system memory pool using memAddToPool( ).
- PCI_MINIMIZE_RESOURCES
- This command is not currently implemented. It specifies that pciAutoConfigLib minimize requirements for memory and I/O space.
- PCI_PSYSTEM_STRUCT_COPY - PCI_SYSTEM * pArg
- This command has been added for ease of converting from the old interface to the new one. This will set each value as specified in the pSystem structure. If the PCI_SYSTEM structure has already been filled, the pciAutoConfig(pSystem) call can be changed to:
void *pCookie; pCookie = pciAutoConfigLibInit(NULL); pciAutoCfgCtl(pCookie, PCI_PSYSTEM_STRUCT_COPY, (void *)pSystem); pciAutoCfgFunc(pCookie);The fields of the PCI_SYSTEM structure are defined below. For more information about each one, see the paragraphs above and the documentation for pciAutoConfigLib.
- pciMem32
- Specifies the 32-bit prefetchable memory pool base address.
- pciMem32Size
- Specifies the 32-bit prefetchable memory pool size.
- pciMemIo32
- Specifies the 32-bit non-prefetchable memory pool base address.
- pciMemIo32Size
- Specifies the 32-bit non-prefetchable memory pool size
- pciIo32
- Specifies the 32-bit I/O pool base address.
- pciIo32Size
- Specifies the 32-bit I/O pool size.
- pciIo16
- Specifies the 16-bit I/O pool base address.
- pciIo16Size
- Specifies the 16-bit I/O pool size.
- includeRtn
- Specifies the device inclusion routine.
- intAssignRtn
- Specifies the interrupt assignment routine.
- autoIntRouting
- Can be set to TRUE to configure pciAutoConfig( ) only to call the BSP interrupt routing routine for devices on bus number 0. Setting autoIntRoutine to FALSE will configure pciAutoConfig( ) to call the BSP interrupt routing routine for every device regardless of the bos on which the device resides.
- bridgePreInit
- Specifies the bridge initialization routine to call before initializing devices on the bus that the bridge implements.
- bridgePostInit
- Specifies the bridge initialization routine to call after initializing devices on the bus that the bridge implements.
EINVAL if pCookie is not NULL or cmd is not recognized
OK, or ERROR if the command or argument is invalid.
pciAutoDevReset( ) - Quiesce a PCI device and reset all writeable status bits.
STATUS pciAutoDevReset ( PCI_LOC * pPciLoc /* device to be reset */ )
This routine turns off a PCI device by disabling the Memory decoders, I/O decoders, and Bus Master capability. The routine also resets all writeable status bits in the status word that follows the command word sequentially in PCI config space by performing a longword access.
OK, always.
pciAutoBusNumberSet( ) - Set the primary, secondary, and subordinate bus number.
STATUS pciAutoBusNumberSet ( PCI_LOC * pPciLoc, /* device affected */ UINT primary, /* primary bus specification */ UINT secondary, /* secondary bus specification */ UINT subordinate /* subordinate bus specification */ )
This routine sets the primary, secondary, and subordinate bus numbers for a device that implements the Type 1 PCI Configuration Space Header.
This routine has external visibility to enable it to be used by BSP Developers for initialization of PCI Host Bridges that may implement registers similar to those found in the Type 1 Header.
OK, always.
pciAutoFuncDisable( ) - Disable a specific PCI function.
void pciAutoFuncDisable ( PCI_LOC * pPciFunc /* input: Pointer to PCI function struct */ )
This routine clears the I/O, mem, master, & ROM space enable bits for a single PCI function.
The PCI spec says that devices should normally clear these by default after reset but in actual practice, some PCI devices do not fully comply. This routine ensures that the devices have all been disabled before configuration is started.
N/A.
pciAutoFuncEnable( ) - Perform final configuration and enable a function.
void pciAutoFuncEnable ( PCI_SYSTEM * pSys, /* for backwards compatibility */ PCI_LOC * pFunc /* input: Pointer to PCI function structure */ )
Depending upon whether the device is included, this routine initializes a single PCI function as follows:
Initialize the cache line size register Initialize the PCI-PCI bridge latency timers Enable the master PCI bit for non-display devices Set the interrupt line value with the value from the BSP.
N/A.
pciAutoGetNextClass( ) - find the next device of specific type from probe list.
STATUS pciAutoGetNextClass ( PCI_SYSTEM * pSys, /* for backwards compatibility */ PCI_LOC * pPciFunc, /* output: Contains the BDF of the device found */ UINT * index, /* Zero-based device instance number */ UINT pciClass, /* class code field from the PCI header */ UINT mask /* mask is ANDed with the class field */ )
The function uses the probe list which was built during the probing process. Using configuration accesses, it searches for the occurrence of the device subject to the class and mask restrictions outlined below. Setting class to zero and mask to zero allows searching the entire set of devices found regardless of class.
TRUE if a device was found, else FALSE.
pciAutoRegConfig( ) - Assign PCI space to a single PCI base address register.
UINT pciAutoRegConfig ( PCI_SYSTEM * pSys, /* backwards compatibility */ PCI_LOC * pPciFunc, /* Pointer to function in device list */ UINT baseAddr, /* Offset of base PCI address */ UINT nSize, /* Size and alignment requirements */ UINT addrInfo /* PCI address type information */ )
This routine allocates and assigns PCI space (either memory or I/O) to a single PCI base address register.
Returns (1) if BAR supports mapping anywhere in 64-bit address space. Returns (0) otherwise.
pciAutoAddrAlign( ) - Align a PCI address and check boundary conditions.
STATUS pciAutoAddrAlign ( UINT32 base, /* base of available memory */ UINT32 limit, /* last addr of available memory */ UINT32 reqSize, /* required size */ UINT32 * pAlignedBase /* output: aligned address put here */ )
OK, or ERROR if available memory has been exceeded.
pciAutoConfig( ) - Automatically configure all nonexcluded PCI headers. Obsolete.
void pciAutoConfig ( PCI_SYSTEM * pSystem /* PCI system to configure */ )
This routine is obsolete. It is included for backward compatibility only. It is recommended that you use the pciAutoCfg( ) interface instead of this one.
Top level function in the PCI configuration process.
For all nonexcluded PCI functions on all PCI bridges, this routine will automatically configure the PCI configuration headers for PCI devices and subbridges. The fields that are programmed are:
1. Status register. 2. Command Register. 3. Latency timer. 4. Cache Line size. 5. Memory and/or I/O base address and limit registers. 6. Primary, secondary, subordinate bus number (for PCI-PCI bridges). 7. Expansion ROM disable. 8. Interrupt Line.
Probe PCI config space and create a list of available PCI functions. Call device exclusion function, if registered, to exclude/include device. Disable all devices before we initialize any. Allocate and assign PCI space to each device. Calculate and set interrupt line value. Initialize and enable each device.
N/A.
sysPciAutoConfig( ) - PCI autoConfig support routine
void sysPciAutoConfig (void)
This routine instantiates the PCI_SYSTEM structure needed to configure the system. This consists of assigning address ranges to each category of PCI system resource: Prefetchable and Non-Prefetchable 32-bit Memory, and 16- and 32-bit I/O. The "MASK_PCI_xxx_BITS is dependant on the memory map, (i.e. if CHRP_ADRS_MAP is defined). Global values for the Cache Line Size and Maximum Latency are also specified. Finally, the four supplemental routines for device inclusion/exclusion, interrupt assignment, and pre- and post-enumeration bridge initialization are specified.
CPU Space PCI Space (these are the values used
for autoconfig setup)
PReP Mapping 0x80000000 ----------------- ISA_MSTR_IO_BUS
| ISA LEGACY | 0x80004000 ----------------- ISA_MSTR_IO_BUS + ISA_LEGACY_SIZE
| PCI 16-bit I/O | 0x81010000 -----------------
| Unused | 0x81000000 ----------------- PCI_MSTR_IO_BUS
| PCI 32-bit I/O | 0x81800000 -----------------
: :0xC1000000 ----------------- PCI_MSTR_MEMIO_BUS
| NPREF PCI MEM | 0xC5000000 ----------------- PCI_MSTR_MEM_BUS
| PCI 32-bit MEM | 0xC5800000 -----------------
CHRP Mapping 0x80000000 ----------------- PCI_MSTR_MEMIO_BUS
| PCI 32-bit MEM | 0x84000000 ----------------- PCI_MSTR_MEM_BUS
| NPREF PCI MEM | 0x84800000 -----------------
: :0xFE000000 ----------------- ISA_MSTR_IO_BUS
| ISA LEGACY | 0xFE004000 ----------------- ISA_MSTR_IO_BUS + ISA_LEGACY_SIZE
| PCI 16-bit I/O | 0xFE800000 ----------------- PCI_MSTR_IO_BUS
| PCI 32-bit I/O | 0xFEC00000 -----------------
N/A
sysDec2155xInit( ) - initialize registers of the Dec2155x (Drawbridge) chip
STATUS sysDec2155xInit (void)
This routine initializes registers of the DEC 2155x PCI-to-PCI bridge and maps access to the Compact PCI bus.
OK on success, else ERROR (Dec2155x not in correct state).
sysDec2155xAdrsGet( ) - capture and save the base address of the dec2155x csr
void sysDec2155xAdrsGet (void)
This routine reads the base address of the Dec2155x CSR BAR assigned during PCI auto-configuration, translates the address to the equivalent CPU address and saves the results for later use.
N/A
sysDec2155xInit2( ) - perform phase 2 Dec2155x initialization
void sysDec2155xInit2 (void)
This routine performs the initialization that must be performed after PCI auto-configuration.
N/A
sysDec2155xIntClear( ) - clear a Dec2155x internal interrupt
STATUS sysDec2155xIntClear ( int vector /* interrupt vector for interrupt */ )
This routine clears the specified internal Dec2155x interrupt.
OK, or ERROR if invalid interrupt vector.
sysLib, sysDec2155xIntEnable( )
sysDec2155xBusIntGen( ) - generate an out-bound cPCI bus interrupt
STATUS sysDec2155xBusIntGen ( int level, /* interrupt level to generate (not used) */ int vector /* interrupt vector for interrupt */ )
This routine generates a Compact PCI backpanel interrupt by setting one of the 16 bits in the 2155x Primary Set IRQ register. The bit is set regardless of the current state of the bit and whether the interrupt has been enabled by the host processor. Because the Compact PCI bus does not have interrupt levels or vectors, the caller's interrupt level parameter is ignored and the caller's vector number is used to select the bit to set in the Primary Set IRQ Register. The symbol DEC2155X_DOORBELL0_INT_VEC corresponds to bit 0 (LSB) and the remaining bits are mapped in sequence.
OK, or ERROR if vector is out of range.
sysLib, sysBusIntAck( )
sysDec2155xIntDisable( ) - disable a Dec2155x internal interrupt
STATUS sysDec2155xIntDisable ( int vector /* interrupt vector for interrupt */ )
This routine disables the specified internal Dec2155x interrupt.
OK, or ERROR if invalid interrupt vector.
sysLib, sysDec2155xIntEnable( )
sysDec2155xIntEnable( ) - Enable a Dec2155x internal interrupt
STATUS sysDec2155xIntEnable ( int vector /* interrupt vector for interrupt */ )
This routine enables the specified internal Dec2155x interrupt.
OK, or ERROR if invalid interrupt vector.
sysLib, sysDec2155xIntDisable( )
sysDec2155xErrClr( ) - Dec2155x Error Clear routine
void sysDec2155xErrClr (void)
This is the Error clear routine for the Dec21554x PCI to PCI Bridge. The following error bits are cleared:
Secondary Status Register: Data Parity Detected Signaled Target Abort Received Target Abort Received Master Abort Signaled System Error Detected Parity Error
Primary Status Register: Received Master Abort
Chip Status Register: Upstream Delayed Transaction Master Timeout Upstream Delayed Read Transaction Discarded Upstream Delayed Write Transaction Discarded Upstream Posted Write Data Discarded
N/A
sysDec2155xIntr( ) - Dec2155x (Drawbridge) PCI-to-PCI interrupt handler
void sysDec2155xIntr (void)
This is the interrupt handler for the Dec2155x PCI-to-PCI Bridge. It is connected to the single Dec2155x interrupt from the interrupt controller and examines the Dec2155x chip to determine the interrupt number of the interrupt source. Having obtained the interrupt number, this routine then indexes into the system vector table and dispatches the specified interrupt handling routine(s).
The Dec2155x does not present a vector number. Each interrupt source within the chip is examined to determine the interrupt source and a logical interrupt vector number is synthesized as a result of that search. The search order is as follows:
Power Management Transition to D0 (due to response time requirements) Secondary doorbell interrupts I20 interrupt Upstream Memory 2 BAR page crossing interrupts.
This handler will clear all interrupt sources except the Upstream Memory 2 BAR page crossing interrupts. Since there are 64 of these interrupts, it is left to the page crossing handler to clear the interrupts it services. This policy eliminates races in determining which page crossing interrupts were presented in time for the handler to see them vs. those that arrived too late for processing. The only exception to this policy in the case of a page crossing interrupt arriving without a registered handler. This is a programming error, but to protect itself, the interrupt handler will clear any pending page crossing interrupts before reporting the un-handled interrupt.
N/A
sysDec2155xChkEnables( ) - check the originating and target bus enables
STATUS sysDec2155xChkEnables ( UINT32 origOffset, UINT32 trgtOffset, UINT32 adrsSpace )
This routine examines the states of the I/O or Memory enables on the originating bus and the Master Enable on the target bus. Both must be enabled before the Dec2155x can pass a transaction across to the opposite bus.
OK if the bridge is active, else ERROR
sysLib, sysLocalToBusAdrs( ), sysBusToLocalAdrs( ), sysDec2155xCnvrtAdrs( )
sysPciConfig21554InLong( ) - Perform Dec21554 long input configuration access
STATUS sysPciConfig21554InLong ( int busNo, /* bus number */ int deviceNo, /* device number */ int funcNo, /* function number */ int offset, /* offset into the configuration space */ UINT32 * pData /* data read from the offset */ )
This function peforms a Dec21554 style long input configuration access on the input bus, device, and function using the passed in offset.
OK if configuration access succeeded ERROR of configuration access failed
sysModel( ) - return the model name of the CPU board
char * sysModel (void)
This routine returns the model name of the CPU board. The returned string depends on the board model and CPU version being used, for example, "Motorola MVME2600 - MPC 604e".
A pointer to the string.
sysBspRev( ) - return the BSP version and revision number
char * sysBspRev (void)
This routine returns a pointer to a BSP version and revision number, for example, 1.1/0. BSP_REV is concatenated to BSP_VERSION and returned.
A pointer to the BSP version/revision string.
sysDecDelay( ) - decrementer delay
void sysDecDelay ( UINT usDelay )
This function's purpose is delay for the specified number micro-seconds.
none
sysHwInit( ) - initialize the system hardware
void sysHwInit (void)
This routine initializes various features of the CPU board. It is called by usrInit( ) in usrConfig.c. This routine sets up the control registers and initializes various devices if they are present.
This routine should not be called directly by the user application. It cannot be used to initialize interrupt vectors.
N/A
sysPhysMemTop( ) - get the address of the top of physical memory
char * sysPhysMemTop (void)
This routine returns the address of the first missing byte of memory, which indicates the top of memory.
Normally, the user specifies the amount of physical memory with the macro LOCAL_MEM_SIZE in config.h. BSPs that support run-time memory sizing do so only if the macro LOCAL_MEM_AUTOSIZE is defined. If not defined, then LOCAL_MEM_SIZE is assumed to be, and must be, the true size of physical memory.
Do no adjust LOCAL_MEM_SIZE to reserve memory for application use. See sysMemTop( ) for more information on reserving memory.
The address of the top of physical memory.
sysMemTop( ) - get the address of the top of VxWorks memory
char * sysMemTop (void)
This routine returns a pointer to the first byte of memory not controlled or used by VxWorks.
The user can reserve memory space by defining the macro USER_RESERVED_MEM in config.h. This routine returns the address of the reserved memory area. The value of USER_RESERVED_MEM is in bytes.
The address of the top of VxWorks memory.
sysToMonitor( ) - transfer control to the ROM monitor
STATUS sysToMonitor ( int startType /* parameter passed to ROM to tell it how */ /* to boot */ )
This routine transfers control to the ROM monitor. Normally, it is called only by reboot( )--which services ^X--and by bus errors at interrupt level. However, in some circumstances, the user may wish to introduce a startType to enable special boot ROM facilities.
Does not return.
sysHwInit2( ) - initialize additional system hardware
void sysHwInit2 (void)
This routine connects system interrupt vectors and configures any required features not configured by sysHwInit( ).
N/A
sysProcNumGet( ) - get the processor number
int sysProcNumGet (void)
This routine returns the processor number for the CPU board, which is set with sysProcNumSet( ).
The processor number for the CPU board.
sysLib, sysProcNumSet( )
sysProcNumSet( ) - set the processor number
void sysProcNumSet ( int procNum /* processor number */ )
This routine sets the processor number for the CPU board. Processor numbers should be unique on a single backplane. It also maps local resources onto the VMEbus.
N/A
sysLib, sysProcNumGet( )
sysLocalToBusAdrs( ) - convert a local CPU address to a PCI bus address
STATUS sysLocalToBusAdrs ( int adrsSpace, /* bus address space where busAdrs resides */ char * localAdrs, /* local address to convert */ char * * pBusAdrs /* where to return bus address */ )
Given a CPU address, this routine returns a corresponding local PCI bus or Compact (backpanel) PCI bus address provided that such an address exists. The target PCI bus (local or backpanel) is selected by the adrsSpace parameter. Legal values for this parameter are found in "pci.h". If a transparent bridge is used to access the Compact PCI bus, the local PCI bus and the backpanel PCI bus share the same address space. In this case, the local and backpanel address space designators are synonomous.
OK, or ERROR if the address space is unknown or the mapping is not possible.
sysBusToLocalAdrs( ) - convert a PCI bus address to a local CPU address
STATUS sysBusToLocalAdrs ( int adrsSpace, /* bus address space where busAdrs resides */ char * busAdrs, /* bus address to convert */ char * * pLocalAdrs /* where to return local address */ )
Given a local or Compact (backpanel) PCI address, this routine returns a corresponding local CPU bus address provided such an address exists. The originating PCI bus (local or backpanel) is selected by the adrsSpace parameter. Legal values for this parameter are found in "pci.h". If a transparent bridge is used to access the Compact PCI bus, the local PCI bus and the Compact PCI bus share the same address space. In this case, the local and backpanel address space designators are synonomous.
OK, or ERROR if the address space is unknown or the mapping is not possible.
sysBusTas( ) - test and set a location across the bus
BOOL sysBusTas ( char * adrs /* address to be tested and set */ )
The cPCI bridge chips do not support PCI target locking, therefore there is no atomic RMW operation. This routine performs a software-based mutual exclusion algorithm in place of a true test and set.
This algorithm is performed through a PCI-to-PCI bridge to a shared location that is subject to unprotected access by multiple simultaneous processors. There is the possibility that the bridge will deliver a delayed read completion to a PCI bus master which was not the original initiator of the delayed read. The bridge delivers the delayed read completion to the new requestor because it believes that the new delayed read request is actually the original master performing a delayed read retry as required by the PCI spec. When the original master comes back with the genuine retry, the bridge treats it as a new request. When this "aliasing" occurs, a read performed after a write can appear to complete ahead of the write, which is in violation of PCI transaction ordering rules. Since this algorithm depends on a strict time-ordered sequence of operations, it can deadlock under this condition. To prevent the deadlock, a throw-away read must be performed after the initial write. Since the bridge only remembers once instance of a queued delayed read request, the throw-away read will "consume" the results of a mis-directed read completion and subsequent read requests are guaranteed to be queued and completed after the write.
TRUE if lock acquired. FALSE if lock not acquired.
sysLib, sysBusTasClear( )
sysBusTasClear( ) - clear a location set by sysBusTas( )
void sysBusTasClear ( volatile char * address /* address to be tested-and-cleared */ )
This routine clears a bus test and set location. This routine is only required if the sysBusTas( ) routine uses special semaphore techniques (such as bus locking). Since the sysBusTas routine doesn't use any special semaphore techniques, this routine is a no-op.
If used, the BSP activates this routine by placing its address into the global variable smUtilTasClearRtn.
N/A
sysNvRead( ) - read one byte from NVRAM
UCHAR sysNvRead ( ULONG offset /* NVRAM offset to read the byte from */ )
This routine reads a single byte from a specified offset in NVRAM. (User I2C SROM).
The byte from the specified NVRAM offset.
sysNvWrite( ) - write one byte to NVRAM
void sysNvWrite ( ULONG offset, /* NVRAM offset to write the byte to */ UCHAR data /* datum byte */ )
This routine writes a single byte to a specified offset in NVRAM. (User I2C SROM).
N/A
sysCpuCheck( ) - confirm the CPU type
void sysCpuCheck (void)
This routine validates the cpu type. If the wrong cpu type is discovered a message is printed using the serial channel in polled mode.
N/A.
sysProbeErrClr( ) - clear errors associated with probing an address on a bus.
void sysProbeErrClr (void)
This routine clears the error flags and conditions in the DAR, DSISR, SRR0 and SRR1 PowerPC registers arising from probing addresses as well as the PCI_CFG_STATUS registers and the Universe PCI_CSR and V_AMERR registers.
N/A
sysPciProbe( ) - probe a PCI bus address
STATUS sysPciProbe ( char * adrs, /* address to be probed */ int mode, /* VX_READ or VX_WRITE */ int length, /* 1, 2 or 4 byte probe */ char * pVal /* address of value to write OR address of */ /* location to place value read */ )
This routine probes an address on the PCI bus. The PCI bridge chip must have a special setup to enable generation of Master Abort cycles on write probes and reception of Target Abort cycles on read probes. The CPU must be configured to enable Machine Check exceptions. In addition, if the probe is a write, the Universe must be configured to disable Posted Writes. All probing is done with interrupts disabled.
OK or ERROR if address cannot be probed
sysBusProbe( ) - probe a bus address based on bus type.
STATUS sysBusProbe ( char * adrs, /* address to be probed */ int mode, /* VX_READ or VX_WRITE */ int length, /* 1, 2 or 4 byte probe */ char * pVal /* address of value to write OR address of */ /* location to place value read */ )
This routine is a function hook into vxMemProbe. It determines which bus, PCI or local is being probed based on the address to be probed. If the PCI bus is being probed, the sysPciProbe( ) routine is called to do the special PCI probing. If the local bus is being probed, the routine calls an architecture-specific probe routine.
ERROR if the probed address does not respond or causes a MMU fault. Returns OK if the probed address responds.
sysUsDelay( ) - delay at least the specified amount of time (in microseconds)
void sysUsDelay ( UINT32 delay /* length of time in microsec to delay */ )
This routine will delay for at least the specified amount of time using the lower 32 bit "word" of the Time Base register as the timer. The accuracy of the delay increases as the requested delay increases due to a certain amount of overhead. As an example, a requested delay of 10 microseconds is accurate within approximately twenty percent, and a requested delay of 100 microseconds is accurate within approximately two percent.
This routine will not relinquish the CPU; it is meant to perform a busy loop delay. The minimum delay that this routine will provide is approximately 10 microseconds. The maximum delay is approximately the size of UINT32; however, there is no roll-over compensation for the total delay time, so it is necessary to back off two times the system tick rate from the maximum.
N/A
sysDebugMsg( ) - print a debug string to the console in polled mode.
void sysDebugMsg ( char * str, UINT32 recovery )
This routine prints a message to the system console in polled mode and optionally exits to the monitor.
N/A
sysPciInsertLong( ) - Insert field into PCI data long
void sysPciInsertLong ( UINT32 adrs, /* PCI address */ UINT32 bitMask, /* Mask which defines field to alter */ UINT32 data /* data written to the offset */ )
This function writes a field into a PCI data long without altering any bits not present in the field. It does this by first doing a PCI long read (into a temporary location) of the PCI data long which contains the field to be altered. It then alters the bits in the temporary location to match the desired value of the field. It then writes back the temporary location with a PCI long write. All PCI accesses are byte and the field to alter is specified by the "1" bits in the bitMask parameter.
N/A
sysPciInsertWord( ) - Insert field into PCI data word
void sysPciInsertWord ( UINT32 adrs, /* PCI address */ UINT16 bitMask, /* Mask which defines field to alter */ UINT16 data /* data written to the offset */ )
This function writes a field into a PCI data word without altering any bits not present in the field. It does this by first doing a PCI word read (into a temporary location) of the PCI data word which contains the field to be altered. It then alters the bits in the temporary location to match the desired value of the field. It then writes back the temporary location with a PCI word write. All PCI accesses are word and the field to alter is specified by the "1" bits in the bitMask parameter.
N/A
sysPciInsertByte( ) - Insert field into PCI data byte
void sysPciInsertByte ( UINT32 adrs, /* PCI address */ UINT8 bitMask, /* Mask which defines field to alter */ UINT8 data /* data written to the offset */ )
This function writes a field into a PCI data byte without altering any bits not present in the field. It does this by first doing a PCI byte read (into a temporary location) of the PCI data byte which contains the field to be altered. It then alters the bits in the temporary location to match the desired value of the field. It then writes back the temporary location with a PCI byte write. All PCI accesses are byte and the field to alter is specified by the "1" bits in the bitMask parameter.
N/A
sysPciOutByteConfirm( ) - Byte out to PCI memory space and flush buffers.
void sysPciOutByteConfirm ( UINT32 adrs, /* PCI address */ UINT8 data /* data to be written */ )
This function outputs a byte to PCI memory space and then flushes the PCI write posting buffers by reading from the target address. Since the PCI spec requires the completion of posted writes before the completion of delayed reads, when the read completes, the write posting buffers have been flushed.
If the write is performed through a PCI-to-PCI bridge to a shared location that is subject to unprotected access by multiple simultaneous processors, there is the possibility that the bridge will deliver a delayed read completion to a PCI bus master which was not the original initiator of the delayed read. When this occurs, it appears as if a PCI delayed read had passed a posted write, which would violate PCI transaction ordering rules. If this is a concern, an additional read must be performed outside of this routine to guarantee that the confirming read performed in this routine was not aliased.
N/A
sysPciOutWordConfirm( ) - Word out to PCI memory space and flush buffers.
void sysPciOutWordConfirm ( UINT32 adrs, /* PCI address */ UINT16 data /* data to be written */ )
This function outputs a word to PCI memory space and then flushes the PCI write posting buffers by reading from the target address. Since the PCI spec requires the completion of posted writes before the completion of delayed reads, when the read completes, the write posting buffers have been flushed.
If the write is performed through a PCI-to-PCI bridge to a shared location that is subject to unprotected access by multiple simultaneous processors, there is the possibility that the bridge will deliver a delayed read completion to a PCI bus master which was not the original initiator of the delayed read. When this occurs, it appears as if a PCI delayed read had passed a posted write, which would violate PCI transaction ordering rules. If this is a concern, an additional read must be performed outside of this routine to guarantee that the confirming read performed in this routine was not aliased.
N/A
sysPciOutLongConfirm( ) - Long word out to PCI memory space and flush buffers.
void sysPciOutLongConfirm ( UINT32 adrs, /* PCI address */ UINT32 data /* data to be written */ )
This function outputs a long word to PCI memory space and then flushes the PCI write posting buffers by reading from the target address. Since the PCI spec requires the completion of posted writes before the completion of delayed reads, when the read completes, the write posting buffers have been flushed.
If the write is performed through a PCI-to-PCI bridge to a shared location that is subject to unprotected access by multiple simultaneous processors, there is the possibility that the bridge will deliver a delayed read completion to a PCI bus master which was not the original initiator of the delayed read. When this occurs, it appears as if a PCI delayed read had passed a posted write, which would violate PCI transaction ordering rules. If this is a concern, an additional read must be performed outside of this routine to guarantee that the confirming read performed in this routine was not aliased.
N/A
sysAtuInit( ) - initialize ATU
STATUS sysAtuInit (void)
This function's purpose is to initialize the address translation unit for use by the operating system.
Ok always
sysIntDisable( ) - disable a bus interrupt level (vector)
STATUS sysIntDisable ( int intLevel /* interrupt level (vector) */ )
This routine disables reception of a specified local or Compact PCI bus interrupt. If the interrupt level (vector) specified is used for shared memory interrupts, a distributed shared memory interrrupt routine is called to disable shared memory interrupts from all PCI or cPCI shared memory devices. If the level (vector) is not the one used for shared memory, the standard intDisable function is called to disable the interrupt at the MPIC.
The results of sysSmIntDisable or intDisable.
sysLib, sysSmIntDisable, sysIntEnable( )
sysIntEnable( ) - enable a bus interrupt level (vector)
STATUS sysIntEnable ( int intLevel /* interrupt level (vector) */ )
This routine enables reception of a specified local or Compact PCI bus interrupt. If the interrupt level (vector) specified is used for shared memory interrupts, a distributed shared memory interrrupt routine is called to enable shared memory interrupts from all PCI or cPCI shared memory devices. If the level (vector) is not the one used for shared memory, the standard intEnable function is called to enable the interrupt at the MPIC.
The results of sysSmIntEnable or intEnable.
sysLib, sysSmIntEnable, sysIntDisable( )
sysBusIntAck( ) - acknowledge a bus interrupt
int sysBusIntAck ( int intLevel /* interrupt level to acknowledge */ )
This routine acknowledges a specified Compact PCI bus interrupt level.
This routine is included for BSP compliance only. Since PCI and Compact PCI bus interrupts are routed directly to the interrupt controller, interrupts are re-enabled in the interrupt controller's handler and this routine is a no-op.
NULL.
sysLib, sysBusIntGen( )
sysBusIntGen( ) - generate a bus interrupt
STATUS sysBusIntGen ( int level, /* interrupt level to generate (not used) */ int vector /* interrupt vector for interrupt */ )
This routine generates an out-bound PCI or Compact PCI backpanel interrupt. The method used to generate the interrupt is based on the current configuration and operating mode of the BSP. If the BSP was built with DEC2155X support and the BSP is operating as the (local) PCI Host device, the outbound Compact PCI bus interrupt is generated by calling sysDec2155xBusIntGen which sets a bit in the secondary mailbox register of the 2155x. If the BSP does not contain DEC2155X support or is operating as a PCI Slave device, the outbound PCI interrupt is generated by calling sysMpicBusIntGen which sets a bit in the CPU 1 portion of the MPIC's Inter-Process Interrupt mechanism. The PRPMC750 hardware ties the CPU 1 interrupt line to one of the PCI bus interrupt pins which allows this mechanism to generate PCI bus interrupts.
The results of sysDec2155xBusIntGen or sysMpicBusIntGen.
sysLib, sysBusIntAck( )
sysMailboxConnect( ) - connect a routine to the in-bound mailbox interrupt
STATUS sysMailboxConnect ( FUNCPTR routine, /* routine called at each mailbox interrupt */ int arg /* argument with which to call routine */ )
This routine connects a local interrupt service routine to a operating mode dependent interrupt vector. If DEC2155X driver support was included, then the interrupt handler is connected to the 2155X's interrupt vector.
The mailbox interrupt is DEC2155X_MAILBOX_INT_VEC.
OK, or ERROR if the routine cannot be connected to the interrupt.
sysLib, intConnect( ), sysMailboxEnable( )
sysMailboxEnable( ) - enable the in-bound mailbox interrupt
STATUS sysMailboxEnable ( char * mailboxAdrs /* address of mailbox (ignored) */ )
This routine enables an operating mode dependent in-bound mailbox interrupt. If the BSP was built with DEC2155X support and the BSP is operating as the (local) PCI Host, sysDec2155xIntEnable is called to enable the proper bit in the 2155X's Secondary mailbox register.
The results of sysDec2155xIntEnable
sysLib, sysMailboxConnect( ), sysMailboxDisable( )
sysMailboxDisable( ) - disable the in-bound mailbox interrupt
STATUS sysMailboxDisable ( char * mailboxAdrs /* address of mailbox (ignored) */ )
This routine disables an operating mode dependent in-bound mailbox interrupt. If the BSP was built with DEC2155X support and the BSP is operating as the (local) PCI Host, sysDec2155xIntDisable is called to disable the proper bit in the 2155X's Secondary mailbox register.
The results of sysDec2155xIntDisable
sysLib, sysMailboxConnect( ), sysMailboxEnable( )