VxWorks BSP Reference : prpmc600
prpmc600 - Motorola
This manual entry provides board-specific information necessary to run VxWorks. Before using a board with VxWorks, verify that the board runs in the factory configuration by using vendor-supplied ROMs and jumper settings and checking the RS-232 connection.
This BSP encompasses the PrPMC600 board and the MCG Compact PCI PrPMC Carrier board (PrPMCBASE-001).
The PrPMC600 board is a single-board computer based on the PowerPC MPC8240 microprocessor.
PrPMC600
The BAT registers are not supported in the current cache management strategy.
- Preparing the PrPMCBASE-001 for VxWorks
- In previous non-system cPCI boards, the 21554 non-transparent PCI-to-PCI bridge was configured for software initialization. To address a start-up timing issue under PPC5-Bug, the 21554 is configured for self-initialization as delivered from the factory. Before using the PrPMCBASE-001 with the default VxWorks configuration, the 21554 must be configured for sofware initialization.
The 21554 initialization mode is controlled by bit 2 (LSB=0) of offset 0x31 in an I2C SROM attached to the 21554. The state of this bit can be altered from the BUG command line using the I2C SROM byte editor as follows:
PPC-Bug>srom;d Device Address =$0000A000 (N/Y)? y Reading SROM into Local Buffer..... $00 (&000) 80? <return> $01 (&001) 00? <return> . . Continue to press <return> until byte 0x31 is reached. . $31 (&049) 00? 04 (or 00 for BUG mode) $32 (&050) 00? . Update SROM (Y/N)? y Writing SROM from Local Buffer..... Verifying SROM with Local Buffer...The following symptoms are the result of attempted operation with the wrong 21554 initialization mode:
Env Symptom BUG Everything appears normal, but a "ver" command from the cPCI Host (Mesquite) does not report the presence of a PrPMCBASE-001. VxWorks The mis-configured PrPMCBASE-001 can consume all available PCI allocation space and prevent the proper configuration of other boards in the cPCI chassis. If in doubt, re-build the PCI Host BSP with INCLUDE_SHOW_ROUTINES defined and display the PCI header of the 21554 on the PrPMCBASE-001 using the pciHeaderShow command at the debug console of the PCI Host. If BAR2 and/or BAR3 are non-zero using the pre-built PrPMC BSP binary image, the PrPMCBASE-001 is mis-configured.
The PrPMC600 boards have two sets of flash EEPROM (FLASH). Bank A consists of two 32-pin PLCC sockets which can be populated with up to 1024KB of FLASH memory. It resides at address 0xFFF00000 and is restricted to 8 bits in width. This memory contains Motorola's PPC5-Bug . Bank B may be populated with four 512Kx16 FLASH devices to obtain 4MB of 64-bit wide expansion FLASH memory or four 1Mx16 FLASH devices to obtain 8MB of 64-bit wide FLASH memory. The expansion FLASH memory starts at address 0xFF000000. FLASH is soldered in on the back of the boards. The VxWorks boot kernel resides in the soldered FLASH. See Hardware Details: ROM Considerations for information about loading and writing the boot kernel image to the soldered FLASH.
- Boot Line Parameters
- A limited non-volatile storage capability is implemented using a 256-byte Serial EEPROM (SROM). The entire SROM contents are reserved for storage of the VxWork boot line.
To load VxWorks, and for more information, follow the instructions in the Tornado User's Guide: Getting Started.
The following jumpers are relevant to VxWorks configuration: The PrPMC600 has one bank of four Jumpers (J3).
For details of jumper configuration, see the board diagram at the end of this entry and in the hardware manual.
Jumper Function Description J3 ROM controller Remove the jumper from pins 1 and 2 to select the socketed FLASH. Install the jumper across pins 1 and 2 to select the soldered FLASH. [factory configuration]. J3 User Configurable The 3 remaining jumpers in the J3 jumper bank have no preset function and can be configured by users as necessary. Note that ROM controller jumpers should be set to select socketed FLASH until VxWorks boot code is written to soldered FLASH, after which the jumpers should be restored to the factory configuration of soldered FLASH.
The following subsections list all supported and unsupported features, as well as any feature interaction.
The following features of the PrPMC600 board are supported:
Feature Description Processor MPC8240 (MPC603 based); 66.67 and 83.33MHz bus clock FLASH 1MB socketed (8-bit wide); 4 or 8MB expansion (64-bit wide) DRAM 32 or 64 MB ECC Synchronous DRAM (SDRAM) Memory Model Both CHRP and PReP models are supported Peripherals one 16550-compatible async serial debug port; I82559 10/100Base-TX Ethernet interface PCI Interface 32-bit address, 32-bit data; complies with PCI Local Bus Specification, Revision 2.1
The following features of the PrPMC600 board are not supported:
Feature Description DMA Channels 2 Independent DMA Channels I2O Interface I2O compliant messaging interface PCI Interface 64-bit data
None known.
This section details device drivers and board hardware elements.
The device drivers and libraries included with this BSP are:
i8250Sio - Intel 8250 UART driver (debug port) ppcDecTimer - PowerPC decrementer timer driver (system clock) fei82557End - 10baseT/100baseTX 82559 Ethernet driver dec21x40End - 10baseT/100baseTX DEC 21x4x Ethernet END driver byteNvRam - byte-oriented generic non-volatile RAM driver mpc8240Epic - Motorola Kahlua EPIC interrupt controller driver pciConfigLib - PCI configuration library sysMotI2c - Kahlua I2C high level interface driver sysMpc8240I2c - Kahlua I2C low level interface driver dec2155xCpci - DEC 2155x Non-Transparent PCI-to-PCI Bridge support pciAutoConfigLib - PCI autoconfiguration library pciConfigLib - PCI configuration library pciConfigShow - Show routines of PCI bus library sysMotVpd - Vital Product Data Support sysMotVpdShow - Vital Product Data Show routines sysMotVpdUtil - Vital Product Data Utility routines
This BSP supports the END (Enhanced Network Driver) as the only network interface for Tornado 2.
This BSP supports ECC memory on the PrPMC600. The default configuration is for the ECC support to be enabled. It is strongly recommended that ECC not be disabled. Doing so could cause failures when attempting to boot the kernel, especially if in PReP mode.
On-board RAM for these boards always appears at address 0x0 locally. Dynamic memory sizing is supported. By default, LOCAL_MEM_AUTOSIZE is defined so memory is auto-sized at hardware initialization time. If auto-sizing is not selected, LOCAL_MEM_SIZE must be set to the actual size of DRAM memory available on the board to ensure all memory is available. The default fixed RAM size is set to 16MB (see LOCAL_MEM_SIZE in config.h).The PrPMC600 supports two memory mappings. The default for the PrPMC600 BSP is the CHRP map, the optional mapping is PReP. The mappings are selected by defining or undefining the macro CHRP_ADRS_MAP, which will determine the setting of the ADDRESS_MAP bit in the Kahlua Processor Interface Configuration Register 1. At power-on the bit is configured by sampling the MAA(0) signal. The default hardware/software setup is for CHRP.
The following tables describe the CHRP address mappings. Most of the address maps are fixed by hardware and the base addresses cannot be modified by the user.Table I. CHRP Map From CPU Point of View.
Start Size Access to 0x00000000 LOCAL_MEM_SIZE (16MB min) DRAM LOCAL_MEM_SIZE (0x40000000 - LOCAL_MEM_SIZE) Unused DRAM space 0x40000000 1GB Reserved 0x80000000 0x7CF00000 PCI Memory Space 0xFCF00000 1MB Kahlua registers 0xFD000000 16MB PCI ISA Memory Space 0xFE000000 64KB PCI ISA I/O Space 0xFE800000 4MB PCI I/O Space 0xFEC00000 32MB Configuration Addr Reg. 0xFEE00000 16MB Configuration Data Reg. 0xFEF00000 16MB PCI interrupt Ack. 0xFF000000 8MB 32/64 bit FLASH/ROM Bank 1 0xFFF00000 1MB 8/32/64 bit FLASH/ROM Bank 0 Table II. CHRP Map on PCI Bus.
PCI MEM Space Access Start Size Access to 0x00000000 1GB (max) DRAM space 0x40000000 1GB (fixed) Reserved 0x80000000 2GB-48MB PCI MEM space 0xFCF00000 1MB (fixed) Kahlua registers 0xFD000000 16MB (max) DRAM space 0xFE000000 16MB (fixed) Reserved 0xFF000000 8MB (max) 32/64 bit FLASH ROM space 0xFFF00000 1MB (max) 8/32/64 bit FLASH ROM space
PCI I/O Space Access Start Size Access to 0x00000000 64KB ISA I/O space 0x00010000 8MB-64KB Reserved 0x00800000 4MB PCI I/O space 0x00C00000 4GB-12MB Reserved
The following table describes the modified PowerPC Reference Platform (PReP) address maps created from the CPU point of view. Tornado-compatible mapping deviates only slightly from the model.
Start Size Access to 0x0 LOCAL_MEM_SIZE (16MB min) DRAM LOCAL_MEM_SIZE (0x80000000 - LOCAL_MEM_SIZE) [Not used] 0x80000000 8MB PCI ISA I/O space 0x80800000 8MB Direct PCI Config. Space 0x81000000 (1GB - 32MG) PCI I/O space 0xC0000000 16MB PCI ISA MEM space 0xC1000000 (1GB - 32MG) PCI MEM space 0xFEF00000 1MB Kahlua registers 0xFF000000 8MB 32/64 bit FLASH/ROM Bank 1 0xFFF00000 1MB 8/32/64 bit FLASH/ROM Bank 0
The default pseudo-PReP mapping from the PCI bus point of view is:
PCI MEM Space Access Start Size Access to 0x00000000 16MB (max) PCI ISA MEM space 0x01000000 (1GB - 32MB) PCI MEM space 0x3EF00000 1MB (fixed) Kahlua registers 0x80000000 16MB (min) DRAM space Remember to set LOCAL_MEM_SIZE to the actual amount of DRAM on the board if auto-sizing is not selected.
PCI I/O Space Access Start Size Access to 0x00000000 64KB PCI ISA I/O space 0x00010000 8MB-64KB Reserved 0x00800000 1GB-16MB PCI I/O space 0x3F800000 3GB+8MB Reserved
The PrPMC600 BSP supports shared memory backplane communication with the MCP750 or CPV5000 as the Compact PCI host node. The Wind River documentation provides a great deal of information regarding shared memory concepts. The section below provides tutorial style information regarding the setup of a shared memory system involving the PrPMC600 and either a MCP750 or a CPV5000.
Setting up a working shared memory system involves proper setting of certain "config.h" parameters and proper setting of boot parameters via the "c" command from the boot prompt. There are three components involved in shared memory communication which must be configured properly to create a working system:
The following restrictions apply to shared memory configurations.
- Anchor:
- This is an area of memory which must be accessible to all nodes participating in shared memory backplane communication. The anchor points to the actual shared memory buffer pool which must be located in the same memory space as the anchor itself. The associated "config.h" parameter is SM_ANCHOR_ADRS. In certain configurations, nonzero nodes will "poll" for the location of the anchor. "config.h" defines which comes into play for polling are SM_OFF_BOARD and SYS_SM_SYSTEM_MEM_POLL.
- Master node:
- This node is always designated as node zero. It is the node which sets up the anchor and shared memory pool. Once the anchor and shared memory pool is set up, the master node acts as a peer with the other nodes. The node number (0 in this case) is one of the boot parameters which can be set up with the "c" command from the bootline prompt.
- Sequential addressing:
- This is is governed by a "config.h" parameter, INCLUDE_SM_SEQ_ADDR and is used when sequential IP addresses are assigned to the participating nodes. Node zero is assigned the lowest IP address, followed by nodes 1, 2 etc. which are assigned the subsequent and sequential IP addresses. The advantage of sequential addressing is that fewer boot parameters must be specified to configure the system.
1) Node zero must not boot over the shared memory interface. Only nonzero nodes are allowed to boot over the shared memory "sm" interface. 2) The location of the anchor must be statically determinable by the master node (node 0). That is, the location of the anchor must either be a build-time static parameter or it must be able to be communicated to the master node via the "sm=xxxxxxxx" boot configuration parameter. The nonzero nodes need not know the location of the anchor at build or boot time but can be configured to poll for the anchor dynamically. Below are the crucial "config.h" parameters involved in shared memory:
NOTE: Another piece of shared memory terminology is "host node". The "host node" is the node which configures the compact PCI bus during startup initialization. In a system consisting of an MCP750 and one or more PrPMC600 boards, the "host node" is the MCP750. Don't confuse "host node" with "master node". "Master node" is simply a synonym for "node 0". The "host node" may or may not be the "master node". Note also that the "host node" need not necessarily be a VxWorks node.
Consider a system consisting of an MCP750 (host node) and two PrPMC600 boards. The following six configurations are the only ones possible:
- CPCI_MSTR_MEM_BUS (address):
- The parameter is used to identify the address where the system DRAM will be configured at. This is dependent on the host board used and is defined in "config.h". The explaination says to set the value to 0x80000000 for a MCP750 host (default) or 0x00000000 for a CPV5000 host.
- SM_OFF_BOARD (TRUE or FALSE):
- The parameter has a configurable value of either TRUE or FALSE and directly determines the value of SM_ANCHOR_ADRS (the anchor address).
If SM_OFF_BOARD is defined as FALSE, then the anchor is on-board and SM_ANCHOR_ADRS is defined to be LOCAL_MEM_LOCAL_ADRS + SM_ANCHOR_OFFSET. LOCAL_MEM_LOCAL_ADRS is defined as 0x0 in "config.h" and SM_ANCHOR_OFFSET is defined as 0x4100 in "config.h" to work with an MCP750. SM_ANCHOR_OFFSET needs to be changed to 0x1100 in "config.h" to work with a CPV5000.
If defined as TRUE, then SM_ANCHOR_ADRS is defined as a function call: sysSmAnchorAdrs( ) (defined in "sysLib.c"). This function will dynamically poll, at system startup, various locations (explained below) for the exact location of the shared memory anchor.
Note that if "sm=xxxxxxxx" is used as a boot parameter, then SM_OFF_BOARD has no effect. The value of "xxxxxxxx" will be used as the anchor location regardless of the setting of SM_OFF_BOARD. If simply "sm" is used as a boot parameter, then SM_OFF_BOARD is queried at initialization time to determine if polling is required or not.
- SYS_SM_SYSTEM_MEM_POLL (#define or #undef):
- This define only has an effect if anchor polling is called for (because SM_OFF_BOARD is defined as TRUE and "sm" is used with no "=xxxxxxxx"). In this case, simply defining SYS_SM_SYSTEM_MEM_POLL will cause the node to poll for the anchor at compact PCI bus address CPCI_MSTR_MEM_BUS + SM_ANCHOR_OFFSET (0x80004100). "System memory" (which is the host node's DRAM) will be included as one of the locations where the anchor might reside. Note that other locations may be polled as well (explained later).
Not defining SYS_SM_SYSTEM_MEM_POLL will prevent the polling of system memory for the anchor.
- SYS_SM_ANCHOR_POLL_LIST (#define or #undef):
- This define has an effect only if polling is called for (see SM_OFF_BOARD explained above). When defined, SYS_SM_ANCHOR_POLL_LIST allows a list of devices, identified by device/vendor ID and subsystem ID/subsystem vendor ID to be specified as candidates for the anchor location. Devices which appear directly on the compact PCI bus are found and if they appear on the list defined by SYS_SM_ANCHOR_POLL_LIST, they are checked to see if they house the shared memory anchor. The memory defined by the first memory BAR is queried at offset SM_ANCHOR_OFFSET (0x4100 by default, defined in "config.h"). If SYS_SM_ANCHOR_POLL_LIST is not defined, ALL devices on the compact PCI bus will be considered candidates for the anchor location and will be polled. If SYS_SM_ANCHOR_POLL_LIST defined but empty, NO devices on the compact PCI bus will be considered candidates for the anchor location. In that case, the only location polled would be system memory if SYS_SM_SYSTEM_MEM_POLL (see above) was defined.
- INCLUDE_SM_SEQ_ADDR (#define or #undef)
- If "undef'ed", sequential addressing is disabled. This symbol is defined by default.
Master node on... Anchor on... Sequential Addressing? 1. MCP750 MCP750 NO 2. MCP750 MCP750 YES 3. PrPMC600 MCP750 NO 4. PrPMC600 MCP750 YES 5. PrPMC600 PrPMC600 NO 6. PrPMC600 PrPMC600 YES
Master node on PrPMC600 and Anchor on CPV5000 is not supported.
Below is a description of how each of the above systems would be configured. Crucial "config.h" and boot parameter settings for an example system are given. In each example, SYS_SM_ANCHOR_POLL_LIST was defined to contain information identifying the Dec2155x bridge chip (present on the PrPMC600 board). See "config.h" for the example of how this was done.
1) MCP750 master, MCP750 anchor, no sequential addressing: MCP750: #define SM_OFF_BOARD FALSE #undef SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : dc host name : sunray processor number : 0 inet on ethernet (e) : 124.170.16.112 inet on backplane (b): 124.200.200.1:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : gamma PrPMC600+PrPMCBASE-1: #define SM_OFF_BOARD TRUE #define SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : sm host name : sunray processor number : 1 inet on ethernet (e) : 124.170.16.109 inet on backplane (b): 124.200.200.2 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.1 target name (tn) : alpha PrPMC600+PrPMCBASE-2: (same "config.h" setup as PrPMC600+PrPMCBASE-1 above) boot device : sm host name : sunray processor number : 2 inet on ethernet (e) : 124.170.16.110 inet on backplane (b): 124.200.200.3 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.1 target name (tn) : beta
2) MCP750 master, MCP750 anchor, sequential addressing: MCP750: #define SM_OFF_BOARD FALSE #undef SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : dc host name : sunray processor number : 0 inet on ethernet (e) : 124.170.16.112:ffffff00 inet on backplane (b): 124.200.200.1:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : gamma PrPMC600+PrPMCBASE-1: #define SM_OFF_BOARD TRUE #define SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : sm host name : sunray processor number : 1 inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : target name (tn) : alpha PrPMC600+PrPMCBASE-2: (same "config.h" setup as PrPMC600+PrPMCBASE-1 above) boot device : sm host name : sunray processor number : 2 inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : target name (tn) : beta
3) PrPMC600 master, MCP750 anchor, no sequential addressing: MCP750: #define SM_OFF_BOARD TRUE #define SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : sm host name : sunray processor number : 1 inet on ethernet (e) : 124.170.16.112 inet on backplane (b): 124.200.200.1 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.2 target name (tn) : gamma PrPMC600+PrPMCBASE-1: #define SM_OFF_BOARD FALSE #define SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : er processor number : 0 host name : sunray inet on ethernet (e) : 124.170.16.109 inet on backplane (b): 124.200.200.2:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : alpha PrPMC600+PrPMCBASE-2: #define SM_OFF_BOARD TRUE #define SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : sm processor number : 2 host name : sunray inet on ethernet (e) : 124.170.16.110 inet on backplane (b): 124.200.200.3 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.2 target name (tn) : beta
4) PrPMC600 master, MCP750 anchor, sequential addressing: MCP750: #define SM_OFF_BOARD TRUE #define SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : sm processor number : 1 host name : sunray inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : target name (tn) : gamma PrPMC600+PrPMCBASE-1: #define SM_OFF_BOARD FALSE #define SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : er processor number : 0 host name : sunray inet on ethernet (e) : 124.170.16.109:ffffff00 inet on backplane (b): 124.200.200.1:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : alpha PrPMC600+PrPMCBASE-2: #define SM_OFF_BOARD TRUE #define SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : sm processor number : 2 host name : sunray inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : target name (tn) : beta
5) PrPMC600 master, PrPMC600 anchor, no sequential addressing: MCP750: #define SM_OFF_BOARD TRUE #define SYS_SM_CPCI_BUS_NUMBER 1 #undef SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : sm processor number : 1 host name : sunray inet on ethernet (e) : 124.170.16.112 inet on backplane (b): 124.200.200.1 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.2 user (u) : ball ftp password (pw) (blank = use rsh): flags (f) : 0x0 target name (tn) : gamma PrPMC600+PrPMCBASE-1: #define SM_OFF_BOARD FALSE #define SYS_SM_CPCI_BUS_NUMBER 1 (Not Used) #undef SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : er processor number : 0 host name : sunray inet on ethernet (e) : 124.170.16.109 inet on backplane (b): 124.200.200.2:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : alpha PrPMC600+PrPMCBASE-2: #define SM_OFF_BOARD TRUE #define SYS_SM_CPCI_BUS_NUMBER 1 #undef SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : sm processor number : 2 host name : sunray inet on ethernet (e) : 124.170.16.110 inet on backplane (b): 124.200.200.3 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.2 target name (tn) : beta
6) PrPMC600 master, PrPMC600 anchor, sequential addressing: MCP750: #define SM_OFF_BOARD TRUE #define SYS_SM_CPCI_BUS_NUMBER 1 #undef SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : sm processor number : 1 host name : sunray inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : target name (tn) : gamma PrPMC600+PrPMCBASE-1: #define SM_OFF_BOARD FALSE #define SYS_SM_CPCI_BUS_NUMBER 1 (Not Used) #undef SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : er processor number : 0 host name : sunray inet on ethernet (e) : 124.170.16.109:ffffff00 inet on backplane (b): 124.200.200.1:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : alpha PrPMC600+PrPMCBASE-2: #define SM_OFF_BOARD TRUE #define SYS_SM_CPCI_BUS_NUMBER 1 #undef SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : sm processor number : 2 host name : sunray inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : flags (f) : 0x0 target name (tn) : beta
The system interrupt vector table has 256 entries. Vectors for the various devices on the buses are assigned hierarchically as follows:
The Embedded Programmable Interrupt Controller (EPIC) sets system interrupt priorities and serves as controller of all processor external interrupts. Each of its 16 serial interrupt control registers can be programmed with a relative priority from 15, the highest, to 0, the lowest. A priority of zero effectively disables the interrupt. All of the 16 control registers have been hardwired to a particular interrupt source. The EPIC interrupt controller will operate in the serial interrupt mode.
Vector# Assigned to 00 - 03 EPIC timers 10 - 1f EPIC External interrupts 20 - 2f EPIC Internal interrupts 30 - 3f All EPIC interrupts 40 - 5f [User defined] 60 - 72 Dec2155x interrupts 73 - ff [User defined] The serial interrupt vector numbers and priority assignments are:
For further details, refer to the appropriate board's reference guide.
Vector# EPIC Priority Interrupt Source 30 0 Not Used 31 0 Not Used 32 3 Debug interrupt 33 0 Not Used 34 0 Not Used 35 0 Not Used 36 0 Not Used 37 13 PMC Interrupt A/DEC2155X on PrPMC Carrier 38 14 PMC Interrupt B/I82559 Ethernet 39 13 PMC Interrupt C 3a 13 PMC Interrupt D/DEC21143 on PrPMC Carrier 3b 0 Not Used 3c 0 Not Used 3d 5 16550 UART 3e 4 Front panel Abort Switch 3f 0 Not Used There are only four PCI bus interrupts: A, B, C, and D. They are shared among all PCI bus devices and do not have levels. PCI bus interrupts are wired directly to the EPIC and, therefore, have pre-assigned system vector numbers and interrupt levels. The user enables one or more PCI interrupts and connects vectored ISRs to the system by following these steps:
- 1)
- Identify the PCI interrupt letter(s) as required by the application. Based on this, identify the associated system interrupt level from the following tables:
Primary PCI Bus
----------------
A = PMC_INT_LVL1
B = PMC_INT_LVL2
C = PMC_INT_LVL3
D = PMC_INT_LVL4Secondary PCI Bus
-----------------
A = PMC_INT_LVL4
B = PMC_INT_LVL3
C = PMC_INT_LVL2
D = PMC_INT_LVL1
- 2)
- Define the vector for each PCI interrupt as follows: INT_VEC_IRQ0 + PMC_INT_LVLx where x is 1, 2, 3, or 4, as determined above.
- 3)
- In the application code, perform intConnect( ) for each vector and its associated ISR.
- 4)
- Perform sysIntEnable( ) for each identified system interrupt level.
- 5)
- When the application has finished, perform sysIntDisable( ) for each identified level.
To simplify the addition of PCI-based add-in cards, the BSP provides a PCI auto-configuration library. When INCLUDE_AUTOCONF is defined, the BSP will automatically locate and configure installed PCI devices. When INCLUDE_AUTOCONF is not defined, add-in PCI devices will not be located or configured.If PCI auto-configuration is selected, the auto-cofiguration library will be called from sysHwInit to discover and configure the installed PCI devices and bridges. Device configuration includes the following PCI information:
- Base Address Registers (BARs)
- Space in the address map is dynamically allocated to each valid BAR detected. Allocation pools are maintained for the following PCI address spaces:
16-Bit PCI I/O 32-Bit PCI I/O PCI Memory I/O (non-prefetchable memory) PCI Memory (pre-fetchable)
- Interrupt Routing
- The correct interrupt vector number is placed in the intLine register of the device's PCI header. To connect to the devices's interrupt, simply call intConnect with the value read from intLine.
- PCI Header Completion
- The PCI auto-configuration library fills in the remainder of the PCI header as follows:
Cache Line Size = _CACHE_ALIGN_SIZE/8 Latency Timer = PCI_LAT_TIMER Command Register = I/O enabled, Memory enabled and Bus Master enabled.
- PCI-to-PCI Bridge Configuration
- PCI-to-PCI bridges encountered during PCI auto-configuration will be configured as necessary and devices detected behind the bridge will be configured as described above. Bridge configuration consists of the following:
Primary Bus Number, Secondary Bus Number and Subordinate Bus Number are filled in according to the bridge's position in the system.
I/O Base and Limit registers are configured as required to forward PCI transactions to PCI devices detected and configured beyond the bridge.
Memory Base and Memory Limit registers are configured as required to forward PCI transactions to PCI devices detected and configured beyond the bridge.
Prefetchable Memory Base and Prefetchable Memory Limit are configured as required to forward PCI transactions to PCI devices detected and confured beyond the bridge.
Command Register = I/O enabled, Memory enabled and Bus Master enabled.
Cache Line Size = _CACHE_ALIGN_SIZE/8 Primary Latency Timer = PCI_LAT_TIMER Secondary Latency Timer = PCI_LAT_TIMER
The single serial port on the PrPMC600 board family is implemented as a SCC 16550 UART and is configured as a DTE connection.By default, the serial port is configured as asynchronous, 9600 baud, with 1 start bit, 8 data bits, 1 stop bit, no parity, and no hardware or software handshake. Hardware handshake using RTS/CTS is a supported option.
SCSI is not available on the PrPMC600 board family.
All boards have one Ethernet port which is 10baseT and 100baseTX compatible. The PrPMC600 boards have an RJ45 jack on their front panel for connection to this facility.The Ethernet driver automatically senses and configures the port as 10baseT or 100baseTX.
The Media Access Control (Ethernet) address for each port is obtained from a serial ROM contained in the Ethernet chip. If the address is not found in serial ROM, the driver attempts to read it from Vital Product Data.
If the PrPMC Carrier board is used with the PrPMC600 board, then two ethernet interfaces are available. The primary interface is the I82559 chip onboard the PrPMC600. This is included by default with INCLUDE_FEI_END. The secondary interface is the DEC21143 chip on the PrPMC Carrier board. To boot using the primary interface, use fei0 as the selection for the boot device in the boot parameter list. To boot boot from the secondary ethernet, first, in config.h, define INCLUDE_SECONDARY_ENET and INCLUDE_DEC_END to add DEC21x40 END support. Then rebuild and reflash the bootrom image. Change the boot device entry to be dc1. Also, ensure that an ethernet cable is plugged into the RJ45 connector on the Carrier board.
The 32-bit PCI bus is fully supported under the PCI Local Bus Specification, Revision 2.1. The 64-bit extensions are not supported. All configuration space accesses are made with BDF (bus number, device number, function number) format calls in the pciConfigLib module. For more information, refer to the man pages prpmc600_pciXxx.
This BSP contains support for the Dec2155x non-transparent PCI-to-PCI bridge located on the PrPMCBASE-001 board. This device provides read/write access to and from the Compact PCI bus (cPCI).The following support is provided:
Up to 4 user configurable downstream cPCI to local PCI windows. Up to 2 user configurable upstream local PCI to cPCI windows. Support for in-bound "doorbell" interrupts. Support for cPCI backpanel interrupts. cPCI to local CPU address translation. Local CPU to cPCI address translation. Build-time validation of Dec2155x configuration parameters.
The PReP standard does not support 64-bit PCI addressing. Therefore, this BSP does not provide support for 64-bit addressing through the Dec2155x.There is a limitation when the cPCI to local PCI or cPCI to local CPU address translation routines are presented with a cPCI address which maps into a downstream window on the local board. The translation will succeed and return an address, but when that address is accessed, the Dec2155x will attempt to access one of its own downstream windows. The transfer will fail because PCI devices cannot access themselves on the cPCI bus. Depending on how error detection is configured, the result will be invalid data or a PCI Master Abort.
Interrupt vectors are provided for the interrupts associated with Dec2155x Hot Swap Power State transitions, Intelligent I/O (I2O), and the Upstream Memory 2 Base Address Register but no other support for these features is provided.
During system startup, the Dec2155x must be configured and unlocked before the host enumerates the cPCI bus. To meet this timing requirement, the Dec2155x is configured by the vxWorks boot ROM image. If changes to the Dec2155x configuration are made, new boot ROMs are required in addition to a new kernel. For proper operation, the Dec2155x configuration in the Boot ROMs must match the configuration used by the kernel.
The Dec2155x places certain limitations on window sizes and translation values. This BSP adheres to those limitations and provides build-time parameter checking to help avoid misconfigurations. Modifications to the default Dec2155x configuration provided in this BSP must be made with care to avoid invalid configurations. Information on the default Dec2155x configuration provided by this BSP is presented in the next section and modification guidelines appear later in this entry.
The default Dec2155x configuration supports a host processor (MCP750) and up to 7 cPCI peripheral boards. The following interoperability is supported:
Host access to PrPMC600 CSR and the low 4MB of PrPMC600 DRAM. PrPMC600 access to the low 4MB of host DRAM. PrPMC600 access to peer cPCI boards.
The BSP provides these features using the following Dec2155x configuration:
Primary CSR and Downstream Memory 0 BAR:
Size: 4MB Direction: In-Bound (cPCI to PrPMC600) cPCI Adrs: Dynamic (assigned by host) Local PCI Adrs: PCI_SLV_MEM_BUS (0x80000000 by convention) Local CPU Adrs: PCI_SLV_MEM_LOCAL (0x00000000 by convention) Use: R/W access to CSR (low 4KB) and PrPMC600 DRAM (above 4KB) Upstream I/O or Memory 0 BAR:
Size: 4MB Direction: Out-Bound (PrPMC600 to cPCI) cPCI Adrs: CPCI_MSTR_MEM_BUS (0x80000000 by convention) Local PCI Adrs: Dynamic (assigned by PrPMC600) Local CPU Adrs: Dynamic (based on local PCI adrs) Use: R/W access to host DRAM Upstream Memory 1 BAR:
The remaining Dec2155x Base Address Registers are not used by the BSP and are available for use by the application.
Size: 32MB Direction: Out-Bound (PrPMC600 to cPCI) cPCI Adrs: Base cPCI address of the host's dynamic PCI configuration area (0x00000000 for the default MCP750 BSP) Local PCI Adrs: Dynamic (assigned by PrPMC600) Local CPU Adrs: Dynamic (based on local PCI adrs) Use: R/W access to cPCI devices
Due to the dynamic nature of PCI address allocation, the locations of the upstream Dec2155x windows move as devices are added to the PrPMC600 PCI bus. Since these windows map the cPCI space into the local PrPMC600 PCI and CPU address spaces, their positions determine where the cPCI resources appear when viewed by the PrPMC600 CPU and any PCI devices resident on the PrPMC carrier board. Likewise, the downstream windows move as cPCI devices are added and removed. The downstream windows are used to map the on-board PCI and DRAM resources into the cPCI address space for access by the host and other cPCI devices.To assist with address translation, two translation routines are provided by this BSP:
sysLocalToBusAdrs( ) Translates a local CPU address to an equivalent cPCI or local PCI memory or I/O address. sysBusToLocalAdrs( ) Translates a cPCI or local PCI memory or I/O space address to a local CPU equivalent address.
NOTE: The translations performed by sysLocalToBusAdrs( ) and sysBusToLocalAdrs( ) are not symmetrical if one of the endpoints is the Compact PCI bus. sysLocalToBusAdrs( ) translates by locating a downstream window which makes the local CPU address visible in the cPCI address space. sysBusToLocalAdrs( ) performs a similar operation by locating an upstream window which makes the cPCI address visible in the local CPU address space. Since the two sets of windows map different areas of the local address space, the translation is not reversible.
Due to dynamic PCI address allocation, the PCI address assigned to the Dec2155x CSR area cannot be known until runtime. To determine the assigned address, it is necessary to read the Secondary CSR memory BAR (or the Secondary CSR I/O BAR if I/O space is to be used).The following code fragment derives the CPU address of the Scratchpad 0 register using its PCI memory space address:
UINT32 bar; /* get the contents of the secondary CSR memory BAR (see note below) */ if (pciConfigInLong (0, DEC2155X_PCI_DEV_NUMBER, 0, DEC2155X_CFG_SEC_CSR_MEM_BAR, &bar) != OK) { return (ERROR); } /* calculate the local PCI address of the scratchpad 0 register */ bar += DEC2155X_CSR_SCRATCHPAD0; /* convert the result to the CPU equivalent address */ if (sysBusToLocalAdrs (PCI_SPACE_MEM_PRI, (char *)bar, (char **)&bar) != OK) { return (ERROR); } return (bar);Once the local CPU address is known, the cPCI address can be derived by adding the following code fragment before returning the result:
NOTE: Using the constant DEC2155X_PCI_DEV_NUMBER ensures that the on-board Dec2155x is read. If a search of the local PCI bus had been performed using the Dec2155x device ID, the returned Bus, Device and Function numbers may have corresponded to a Dec2155x part found on an installed PMC card.
if (sysLocalToBusAdrs (PCI_SPACE_MEM_SEC, (char *)bar, (char **)&bar) != OK) return (ERROR); else return (bar);
At start-up, all Dec2155x interrupt sources are masked and cleared. Before unmasking an interrupt, an application ISR service routine must be attached to the appropriate Dec2155x interrupt vector using intConnect( ). Multiple ISR service routines can be connected to each vector if required by the application. Once the handler is attached, the interrupt can be enabled and disabled by calling sysDec2155xIntEnable( ) or sysDec2155xIntDisable( ) as required. Interrupt vector definitions for the Dec2155x internal interrupt sources are defined in prpmc600.h.Unique interrupt vectors are provided for each of the 16 bits in the Dec2155x Secondary IRQ register. Bit 0 (LSB) corresponds to DEC2155X_DOORBELL0_INT_VEC with the remaining bits mapped in sequence. These doorbell interrupts can be used for host-to-PrPMCBASE or PrPMCBASE-to-PrPMCBASE event notification. The Dec2155x interrupt handler clears these interrupts which simplifies the application ISR.
Individual interrupt vectors are also provided for Dec2155x Hot Swap Power State and I2O in-bound list events. The Dec2155x interrupt handler also clears these interrupts.
The 64 Upstream Memory 2 BAR Page Crossing interrupts are all presented on a single interrupt vector and the application ISR is responsible for clearing the bits serviced. Calls to sysDec2155xIntEnable( ) and sysDec2155xIntDisable( ) enable or disable all 64 interrupts.
The Dec2155x interrupt handler provides a default service routine for all unclaimed interrupt vectors, including the Upstream Memory 2 BAR Page Crossing interrupt. The default routine reports the event and clears the interrupt source.
The Dec2155x can generate cPCI backpanel interrupts using any of the bits in the Primary IRQ register if they have been un-masked by the host. The following code fragment generates a compact PCI backpanel interrupt by setting bit 15 (MSB) of the Primary IRQ register:
if (sysBusIntGen (DEC2155X_DOORBELL15_INT_LVL, DEC2155X_DOORBELL15_INT_VEC) != OK) return (ERROR);Note that the cPCI bus does not provide an interrupt vector to the host. The vector number passed to sysBusIntGen( ) simply identifies which bit in the register to set. It is the host's responsibility to locate the interrupt source and clear the interrupt.In config.h: Modify the definition of INTERRUPT_ROUTING_TABLE to match the configuration of your hardware. This table maps PCI IDSEL numbers to MPIC interrupt inputs. The 4 columns in the table map INTA, INTB, INTC and INTD respectively as viewed from the PrPMC site. The default table matches the MCG PrPMCBASE-001 Carrier board.
Modify the definitions of INIT_EXT_SRC0 through INIT_EXT_SRC15 to reflect the desired EPIC interrupt priorities. To disable an interrupt, set it's priority level to 0.
The values of PCI_MSTR_IO_SIZE, PCI_MSTR_MEMIO_SIZE and PCI_MSTR_MEM_SIZE may also require modifications depending on the required PCI dynamic configuration areas required.
Most BSP configuration values are taken from on-board Vital Product Data (VPD) and Serial Presence Detect (SPD) serial EEPROMs. If invalid VPD or SPD information is suspected or reported, defining TOLERATE_CONFIG_ERRORS in config.h may permit operation using default parameters. The use of TOLERATE_CONFIG_ERRORS is intended for use during debug only as it hard-codes non-optimized SDRAM timing and other VPD information. Since the SDRAM timing is configured by the Bootrom, changing the state of TOLERATE_CONFIG_ERRORS requires rebuilding the Bootrom image and re-flashing.
PCI_MSTR_IO_SIZE, PCI_MSTR_MEMIO_SIZE and PCI_MSTR_MEM_SIZE control the sizes of the available PCI address spaces. The windows defined by these parameters must be large enough to accommodate all of the PCI memory and I/O space requests found during PCI autoconfiguration. If they are not, some devices will not be autoconfigured.
By default, the companion MCP750 BSP allocates a 32MB area aligned to a 32MB boundary for dynamic PCI configuration. To access peer PrPMC750 DRAM areas, an upstream window must be opened which matches the size of the host's dynamic PCI configuration area. For translation to work correctly, the host's dynamic PCI configuration area must be aligned to a multiple of the area's size and the corresponding Dec2155x upstream translation register must contain the area's base cPCI address (not CPU address). Since this BSP supports peer-to-peer access between PrPMC750 DRAM areas, the default dynamic PCI configuration area for the PrPMC750 is 64MB aligned to a 64MB boundary which satisfies these requirements.
NOTE: PCI auto-configuration is performed by the bootroms. Any changes to PCI_MSTR_IO_SIZE, PCI_MSTR_MEMIO_SIZE or PCI_MSTR_MEM_SIZE requires the creation of a new bootrom image. In addition to the peer access window, sufficient space must also be available for mapping the host DRAM upstream window and any space required by PrPMCBASE-resident PCI devices. A margin must also be allowed for areas that are unusable due to window alignment requirements.
If the application does not require peer-to-peer PrPMC750 DRAM access, the large 32MB window used to contain the host's dynamic PCI configuration area can be eliminated with a corresponding decrease in the required PrPMC750 dynamic PCI configuration area. If peer-to-peer doorbell interrupts are still required, the doorbell interrupt registers of peer PrPMCBASE boards may be accessed through an I/O window which has much smaller CPU address space requirements. This would require re-configuring the default BSP to access host DRAM through Upstream Memory 1 BAR and using the Upstream I/O or Memory 0 BAR to access the peer PrPMCBASE doorbell interrupt registers.
Altering the Dec2155x configuration requires the careful consideration of several items:
Dec2155x window sizes and alignment. Dec2155x translation values. The size and alignment of the host's dynamic PCI configuration area. The size and alignment of the PrPMC750's dynamic PCI configuration area.
The Dec2155x window parameters are controlled by #defines in config.h. There are three defines associated with each window:
..._SIZE determines the size of the window in bytes and must be an integral power of two. The minimum size for a PCI I/O space window is 64 bytes. The minimum size for a PCI memory space window is 4KB. To disable a window, set the size to 0. Note that the Dec2155x will not allow the Primary CSR and Downstream Memory 0 BAR to be disabled. If the size of this window is set to zero, the Dec2155x will default to a 4KB window. NOTE: If a window value is not a power of 2, or is below the minimum size, sysLib.c will not compile.
..._TYPE determines the type of the window and any placement restrictions. For proper operation, the window must be configured for placement anywhere in the 32-bit PCI address space. The default window sizes can be reduced without altering the sizes of the dynamic PCI configuration area. However, if the required values are significantly reduced from the default values, reducing the size of the dynamic PCI configuration area reduces the size of the MMU page tables at the ratio of 128:1 (a 128KB reduction saves 1KB of MMU table space).
..._TRANS determines the base address of the window on the target PCI bus. It is important to remember that this is a local PCI address (downstream window) or a cPCI address (upstream window). The translation value chosen must be an even multiple if the window size. NOTE: If the translation value is not a multiple of the window size, sysLib.c will not build.
The supported boot devices are:sm - shared memory
er - Primary Ethernet (10baseT or 100baseTX)
dc1 - Secondary Ethernet (10baseT or 100baseTX)Motorola's PPC5-Bug can be used to download and run VxWorks. Consult the relevant user's manuals for details.
The boot methods are affected by the boot parameters. If no password is specified, RSH (remote shell) protocol is used. If a password is specified, FTP protocol is used, or, if the flag is set, TFTP protocol is used.These protocols are used for both Ethernet and shared memory boot devices.
Socketed vs. Soldered ROMs
Pins 1 & 2 of Jumper J3 are used to tell the software whether to boot from the soldered FLASH or not. If the jumper is installed, the code executing from the socketed ROMs will jump to the soldered FLASH and continue execution. If there is nothing in the socketed ROMs, then this jump will not occur and the board will not function.
The factory default is to have the jumper installed which selects the soldered FLASH parts. To make the VxWorks bootrom or PPC5-Bug code run from the socketed ROM parts, the jumper must be removed.
The define FLASH_BOOT in config.h must be setup based on which type of ROM the bootrom will reside in:
if the bootrom will be in Soldered Flash then define FLASH_BOOT. (default) if the bootrom will be in Socketed ROM then undef FLASH_BOOT.
Use the following command sequence on the host to re-make the BSP boot ROM:
cd target/config/prpmc600 make clean make bootrom_uncmp.bin cp bootrom_uncmp.bin /tftpboot/boot.binPower down the board and configure the ROM jumper to select the PPC5-Bug. Connect the Ethernet cable to the 10/100 base T slot on the PrPMCBASE board, then power the board back up.
Before you power-up the PrPMC600, make sure the ROM/FLASH jumper (J3) is set appropriately. This assumes that the PPC5-Bug resides in the ROM selected and that the flashing will occur to the other ROM. To select the Soldered Flash ROM, install a jumper across pins 1 and 2 of J3. To run out of the Socketed ROM, remove the jumper from pins 1 and 2 of J3.The base addresses of the socketed ROM and soldered FLASH are:
Socketed ROM has an address of 0xFFF00000 Soldered FLASH has an address of 0xFF000000At the PPC5-Bug prompt, start the system clock then set up the network transfer from a TFTP host using niot. To start the system clock, the set command must be used. The format is: set MMDDYYhhmm where MM is month, DD is day of month, YY is year, hh is hour (24-hour format), and mm is minutes. This command starts the system clock and sets the current date and time.
PPC5-Bug>set 1016971302Using niot, the Client IP Address, Server IP Address, and Gateway IP Address must be set up for the user's specific environment:
PPC5-Bug>niot Controller LUN =00? Device LUN =00? Node Control Memory Address =00FA0000? Client IP Address =123.123.10.100? 123.321.12.123 Server IP Address =123.123.18.105? 123.321.21.100 Subnet IP Address Mask =255.255.255.0? Broadcast IP Address =255.255.255.255? Gateway IP Address =123.123.10.254? 123.321.12.254 Boot File Name ("NULL" for None) =? . Update Non-Volatile RAM (Y/N)? y PPC5-Bug>The file is transferred from the TFTP host to the target board using the niop command. Important: You must have a TFTP server running on your host's subnet for the niop command to succeed. The file name must be set to the location of the binary file on the TFTP host. The binary file must be stored in the directory identified for TFTP accesses, but the file name is a relative path and does not include the /tftpboot directory name:
PPC5-Bug>niop Controller LUN =00? Device LUN =00? Get/Put =G? File Name =? boot.bin Memory Address =00004000? Length =00000000? Byte Offset =00000000? PPC5-Bug>After the file is loaded onto the target, the "pflash" command is used to put it into socketed ROM or soldered FLASH parts.To put it into socketed ROM:
PPC5-Bug>pflash 4000:fff00 fff00100To put it into soldered FLASH:PPC5-Bug>pflash 4000:fff00 ff000100When the command is finished, power down the board and configure the ROM jumper, change the ethernet connection to the 10/100 base T slot on the PrPMC600 board, then power the board back up.
The value of FLASH_BOOT in config.h must be set appropriately for the bootrom image being flashed, otherwise the bootrom will not execute. See ROM Considerations for more details on setting up FLASH_BOOT correctly.
This section describes miscellaneous information concerning this BSP and its use.
The delivered objects are: bootrom.hex, vxWorks, vxWorks.sym, and vxWorks.st.
The make targets are listed as the names of object-format files. Append .hex to each to derive a hex-format file name.
bootrom bootrom_uncmp bootrom_res_high (bootrom_res does not build) vxWorks (with vxWorks.sym) vxWorks_rom vxWorks.st vxWorks.st_rom vxWorks.res_rom_res_low (vxWorks.res_rom does not build) vxWorks.res_rom_nosym_res_low (vxWorks.res_rom_nosym does not build)
The PrPMC600 doesn't contain an on-board oscillator for generating the processor bus clock. The processor bus clock is generated using a PLL which multiplies the system PCI bus frequency up to create the CPU bus frequency. Since the system PCI bus frequency is not known in advance, the PrPMC600 calculates the CPU bus frequency using the 16550 baud rate clock as a reference. The calculated value (in Hertz) may be accessed using the macro MEMORY_BUS_SPEED which is defined in prpmc600.h.Note that the raw calculated value is returned and may not exactly agree with the expected nominal value. For example, 100 MHz may be returned as 99,999,744 (or 100,000,128) if that was the value calculated. Returning the raw value allows the user to determine the rounding on a case-by-case basis. For example, if the user requires a value rounded to the nearest MHz, the following code fragment could be used:
clkFreqMhz = (MEMORY_BUS_SPEED + 500000)/1000000;
In the routine sysEpicIntHandler (file: mpc8240Epic.c), a sysDecDelay call is required to handle an error condition for Kahlua(MPC8240) Revision 1.0/1.1 chips (Errata #2 on MPC8240 Errata Sheet - Version 1.0.3). The delay is needed to prevent the same interrupt from occurring twice.The PrPMC600 does not provide support for the Flash Bank Select Header on the PrPMC Carrier board. It also does not support the socketed Flash parts on the PrPMC Carrier board
The PrPMC600 does not boot in a backplane where the CPV5000 is the system controller board.
The diagram below shows flash EEPROM locations and jumpers relevant to VxWorks configuration:
For the PrPMC600 board, the 10baseT/100baseTX port appears on the front panel. The debug port is on the side of the board.
PrPMC600 ___________________________________________ | P12 | | ================== | | | | P11 | | ================== | | | | | | | | | | J3 | | 1--2 | | .. | | .. | | 7..8 | | | | | | _ | |-| | | |-| |Serial | |-| |Debug +----+ | |-| |Port X| | | |-| | U| | | |-|_| 1+----+ | | +----+ | | X| | | | U| | | | 2+----+ | | ______ | | | | | |___|____|_________________________________| 10/100 BaseTFor the PrPMCBASE-001 board, the debug and 10baseT/100baseTX ports appear on the front panel.
____________________________________________________________________________ | | | =========== =========== =========== =========== | | | | =========== =========== =========== =========== | | PMC slot 2 PMC slot 1 | | (SYSCON Slot) | | | | +-----+ +-----+ | | |XU2 | |XU1 | | | | | | | | | +-----+ +-----+ | | | | | | | | | | | | | | | | | | | | | | J29 (ROM Ctrl) --> L | | | | | |__.......................___.......................____----___----___----_| PCI Mezzanine Card PCI Mezzanine Card 10/100 Com2 Com1 Cutout Cutout base T Slot Slot 2 1
Key:
| vertical jumper installed
: vertical jumper absent
-- horizontal jumper installed
.. horizontal jumper absent
0 switch off
1 switch on
U three-pin vertical jumper, upper jumper installed
D three-pin vertical jumper, lower jumper installed
L three-pin horizontal jumper, left jumper installed
R three-pin horizontal jumper, right jumper installed
Tornado User's Guide: Getting Started, VxWorks Programmer's Guide: Configuration
Motorola PrPMC600 Programmer's Reference Guide, Motorola Computer Group Online Documentation, http://library.mcg.mot.com/mcg/boards Motorola MPC8240 Integrated Processor User's Manual, Motorola PowerPC 603 RISC Microprocessor User's Manual, Motorola PowerPC Microprocessor Family: The Programming Environments, Intel 82559 Fast Ethernet PCI Bus Controller with Integrated PHY, Intel 82559ER Fast Ethernet PCI Bus Controller with Integrated PHY, DECchip 21143 PCI Fast Ethernet LAN Controller Hardware Reference Manual, Texas Instruments TL16C550C Asynchronous Communications Element Data Sheet, IEEE P1386 Draft 2.0 - Common Mezzanine Card Specification (CMC), IEEE P1386.1 Draft 2.0 - PCI Mezzanine Card Specification (PMC), IEEE P1386.X Draft 0.5 - Processor Mezzanine Specification (PrPMC), Peripheral Component Interconnect (PCI) Local Bus Specification, Rev 2.1, PCI to PCI Bridge Architecture Specification 2.0, PICMG 2.0 D2.14 CompactPCI Specification, Digital Semiconductor 2155x PCI-to-PCI Bridge for Embedded Applications Hardware Reference Manual,