VxWorks BSP Reference : mtx604
mtx60x - Motorola PowerPlus
This reference entry provides board-specific information necessary to run VxWorks. Before using a board with VxWorks, verify that the board runs in the factory configuration by using vendor-supplied ROMs and jumper settings and checking the RS-232 connection.
The Motorola PowerPlus series of boards consists of four families: MVME230x, MVME260x, MVME360x, and MTX60x. This BSP encompasses only the MTX60x family.
The MTX60x board family consists of single-board computers based on the PowerPC 603 and 604 microprocessors. The MTX600 family is a non-VMEbus version of the MVME2600. The series part numbers are of the form:
MTX60p-0nfa
where
p = processor type
3 = MPC603e
4 = MPC604ev
n = number of CPUs
0 = 1 CPU
1 = 2 CPUs
f = feature set
too numerous to itemize
a = not an optionFor example, an MTX604-001a denotes a PowerPC 604ev mother board running at 200 MHz with two PMC site.
The MTX600 boards have two sets of flash EEPROM (FLASH). One set of two AMD Am29F040 FLASH is socketed (sockets XU1 and XU2) and contains Motorola's Open Firmware or, on later revisions, Motorola's PPC1-Bug. The other set of E28f400 FLASH is soldered in. The VxWorks boot kernel resides in the soldered FLASH. See Hardware Details: ROM Considerations for information about loading and writing the boot kernel image to the soldered FLASH.These boards have non-volatile RAM; thus, boot parameters are preserved whenever the system is powered off.
To load VxWorks, and for more information, follow the instructions in the Tornado User's Guide: Getting Started.
The following jumpers are relevant to VxWorks configuration:
For details of jumper configuration, see the board diagram at the end of this entry and in the hardware manual.
MTX60x Jumper Function Description J37 ROM controller Install the jumper across pins 2 and 3 to select the socketed FLASH. Install the jumper across pins 1 and 2 to select the soldered FLASH (factory configuration). Note that ROM controller jumpers should be set to select socketed FLASH until VxWorks boot code is written to soldered FLASH, after which the jumpers should be restored to the factory configuration of soldered FLASH.
The following subsections list all supported and unsupported features, as well as any feature interaction.
The following features of the MTX600 board family are supported:
Feature Description Processors MPC603, MPC604; 33 and 66MHz bus clock L2 Cache 256KB look-aside cache, write-through only FLASH 4 or 8MB soldered (64-bit wide; 8-bit access), 1MB socketed (16-bit wide). Soldered used for VxWorks boot image. DRAM 16, 32, 64, 128, 256MB, two-way interleaved; auto-sized or fixed NVRAM 8KB (MK48T59/559) 8KB Peripherals serial ports COM1 and COM2; two sync/async serial ports; 8-bit single-ended fast SCSI-2 interface; EIDE interface; I2C interface (Philips 8584 for MTX, Falcon two-wire for MTXPlus); AUI and 10baseT/100baseTX Ethernet interface ISA Interface full 64KB memory and I/O space PCI Interface 32-bit address, 32-bit data; complies with PCI Local Bus Specification, Revision 2.1 Miscellaneous RESET switch
The following board features are not supported:
Feature Description Processors Dual Capability DRAM ECC protection RTC MK48T59/559; only NVRAM portion is used Peripherals PS/2 keyboard port; PS/2 mouse port; PS/2 floppy disk port; IEEE1284/printer parallel port ISA Interface ISA RTC and DMA controllers PCI Interface 64-bit data Miscellaneous ABORT switch, 6 status LEDs
None known.
This section details device drivers and board hardware elements.
The device drivers and libraries included with this BSP:
The sl82565IntrCtl module implements the Winbond W83C353 PCI-to-ISA Bridge (PIB) driver. The module was developed originally for the Symphonic Laboratories SL82565 PIB which has been succeeded by the Winbond device.
i8250Sio - Intel 8250 UART driver (serial ports 1 and 2) ppcDecTimer - PowerPC decrementer timer driver (system and timestamp clock) if_dc - 10baseT/100baseTX DEC 21140 Ethernet driver (primary LAN) byteNvRam - byte-oriented generic non-volatile RAM driver sl82565IntrCtl - PIB interrupt controller driver ravenMpic - Motorola Raven MPIC interrupt controller driver pciConfigLib - PCI configuration library z8530Sio - Zilog Z8530 SCC/Z85230 ESCC driver (serial ports 3 and 4) ppcZ8536Timer - Zilog Z8536 timer driver (auxiliary clock) ncr810Lib - NCR 53C875 SCSI controller library ataDrv - EIDE controller driver
On-board RAM for these boards always appears at address 0x0 locally.Dynamic memory sizing is supported. By default, LOCAL_MEM_AUTOSIZE is defined so memory is auto-sized at hardware initialization time. The default fixed RAM size is set to 16MB (see LOCAL_MEM_SIZE in config.h).
The following table describes the modified PowerPC Reference Platform (PReP) address map created from the CPU point of view. Tornado-compatible mapping deviates only slightly from the model.
Start Size Access to 0x0 LOCAL_MEM_SIZE (16MB min) DRAM LOCAL_MEM_SIZE (0x80000000 - LOCAL_MEM_SIZE) [Not used] 0x80000000 64KB PCI ISA I/O space 0x81000000 8MB PCI I/O space 0xC0000000 64KB PCI ISA MEM space 0xC1000000 16MB PCI MEM space 0xD8000000 128MB PCI MEM (max. A32 VME space) 0xE0000000 16MB PCI MEM (A24 VME space) 0xE1000000 0x0EFF0000 [Not used] 0xEFFF0000 64KB PCI MEM (A16 VME space) 0xF0000000 64KB PCI MEM (VME REG. (A32) space) 0xF0010000 0x0BFF0000 [Not used] 0xFC000000 256KB MPIC Reg space 0xFC040000 0x02F40000 [Not used] 0xFEF80000 128KB Falcon/Raven regs. 0xFEFA0000 0x00060000 [Not used] 0xFF000000 16MB ROM space (No PCI)
The following table describes the alternative extended PCI memory address map created from the CPU's point of view. This address mapping is activated by defining EXTENDED_PCI. The intent is to provide a 3GB PCI memory mapping to support the MTXPlus PCI-PCI bridge and user installed PCI cards.
Start Size Access to 0x0 LOCAL_MEM_SIZE (16MB min) DRAM LOCAL_MEM_SIZE (0x40000000 - LOCAL_MEM_SIZE) [Not used] 0x40000000 0xBC000000 PCI MEM space (3GB) 0xFC000000 256KB MPIC Reg space 0xFC040000 0x02F40000 [Not used] 0xFD000000 0x1F80000 PCI I/O space (32MB) 0xFEF80000 128KB Falcon/Raven regs. 0xFEFA0000 0x00060000 [Not used] 0xFF000000 16MB ROM space (No PCI)
The MTX600 does not support Shared Memory because it does not support the VMEbus.
The system interrupt vector table has 256 entries. Vectors for the various devices on the buses are assigned hierarchically as follows:
The specific ISA vector number assignments are:
Vector# Assigned to 00 - 0f ISA IRQ numbers 0 - 15 10 - 1f All MPIC interrupts 20 - 23 Raven timers 24 - 27 Raven interprocessor dispatch 28 Raven detected internal errors 29 - ff [User defined]
Vector numbers not in the table are not used by this BSP.
Vector# Assigned to 02 [Cascade interrupt from PIC2] 03 COM2 04 COM1 09 Aux timers; serial ports 3 and 4 The standard ISA Intel 8259 Programmable Interrupt Controllers (PICs) assert their interrupts through the Raven MPIC as an external interrupt. The external interrupt vector numbers are:
Vector numbers not in the table are not used by this BSP.
Vector# Assigned to 10 ISA PICs 11 Falcon-ECC error 12 PCI Ethernet 13 PCI SCSI 19 PCI PMC1/PMC2 INTA 1a PCI PMC1/PMC2 INTB 1b PCI PMC1/PMC2 INTC 1c PCI PMC1/PMC2 INTD The Raven Multi-Processor Interrupt Controller (MPIC) sets system interrupt priorities and serves as controller of all external interrupts. Each of its 16 interrupt control registers, designated IRQ0 through IRQ15, can be programmed with a relative priority from 15, the highest, to 0, the lowest. A priority of zero effectively disables the interrupt. All but one of the 16 control registers has been hardwired to a particular interrupt source. The IRQ number and priority assignments are as follows:
Note that the z8536 is emulated by a PAL on the MTXPlus. Board fail and Abort interrupts are supported while the CIO interrupt is not. If INCLUDE_MPIC is not defined, there is not Aux Clock support on MTXPlus.
For further details, refer to the appropriate board's reference guide.
Raven MPIC IRQ Priority IRQ Source IRQ0 8 Winbond PIB [all ISA interrupts] IRQ1 0 Falcon ECC Error IRQ2 14 Ethernet IRQ3 3 SCSI IRQ4 0 Graphics [not available] IRQ5 N/A [Not used] IRQ6 N/A [Not used] IRQ7 N/A [Not used] IRQ8 N/A [Not used] IRQ9 0 PCI PMC1/PMC2 INTA IRQ10 13 PCI PMC1/PMC2 INTB IRQ11 2 PCI PMC1/PMC2 INTC IRQ12 0 PCI PMC1/PMC2 INTD IRQ13 0 [Not used] IRQ14 N/A [Not used] IRQ15 N/A [Not used] There are only four PCI bus interrupts: A, B, C, and D. They are shared among all PCI bus devices and do not have levels. PCI bus interrupts are wired directly to the MPIC and, therefore, have pre-assigned system vector numbers and interrupt levels. The user enables one or more PCI interrupts and connects vectored ISRs to the system by following these steps:
- 1)
- Identify the PCI interrupt letter(s) as required by the application. Based on this, identify the associated system interrupt level from the following tables:
Primary PCI Bus
----------------
A = PMC_INT_LVL1
B = PMC_INT_LVL2
C = PMC_INT_LVL3
D = PMC_INT_LVL4Secondary PCI Bus
-----------------
A = PMC_INT_LVL4
B = PMC_INT_LVL3
C = PMC_INT_LVL2
D = PMC_INT_LVL1
- 2)
- Define the vector for each PCI interrupt as follows: INT_VEC_IRQ0 + PMC_INT_LVLx where x is 1, 2, 3, or 4, as determined above.
- 3)
- In the application code, perform intConnect( ) for each vector and its associated ISR.
- 4)
- Perform sysIntEnable( ) for each identified system interrupt level.
- 5)
- When the application has finished, perform sysIntDisable( ) for each identified level.
The MTX600 board family has four serial ports. All are ISA bus devices. Two, serial port 1 (COM1 or console) and serial port 2 (COM2), originate from the PC87308 Super I/O (SIO) chip. The SIO serial ports are functional equivalents to those in an Intel 8250 UART.The other two serial ports, Serial Ports 3 and 4, are implemented in the Zilog Z85230 ESCC chip and the Zilog Z8536 CIO chip (DTR and DSR lines). They can be configured as synchronous serial ports but no support for this mode is provided by this BSP.
By default, all serial ports are configured as asynchronous, 9600 baud, with 1 start bit, 8 data bits, 1 stop bit, no parity, and no hardware or software handshake. Hardware handshake using RTS/CTS is a supported option on all ports.
Only the SCSI-2 bus standard is supported. The MTX600 board family supports an 8-bit SCSI bus.
The MTX600 has both AUI and RJ45 (twisted pair) jack for Ethernet. The RJ45 can be used with either 10baseT or 100baseTX. The Ethernet driver automatically senses and configures the port as 10baseT or 100baseTX. The Ethernet driver is compatible with both DEC21040 and DEC21140 devices.The Media Access Control (Ethernet) address for each port is obtained from a serial ROM contained in the DEC21140 chip. If the address is not found in serial ROM, the driver attempts to read it from NVRAM.
The 32-bit PCI bus is fully supported under the PCI Local Bus Specification, Revision 2.1. The 64-bit extensions are not supported. All configuration space accesses are made with BDF (bus number, device number, function number) format calls in the pciConfigLib module. For more information, refer to the reference entries mv260x_pciXxx.
The default pseudo-PReP mapping from the PCI bus point of view is:
PCI I/O Space Access Start Size Access to 0x00000000 8MB PCI I/O space 0x00000000 64KB ISA I/O space
PCI MEM Space Access Start Size Access to 0x80000000 16MB (min) DRAM space 0x7C000000 256KB (fixed) MPIC REGS
The supported boot devices are:dc - Ethernet (10baseT or 100baseTX or AUI)
Motorola's Open Firmware and PPC1-Bug can be used to download and run VxWorks. Consult the relevant user's manuals for details.
The boot methods are affected by the boot parameters. If no password is specified, RSH (remote shell) protocol is used. If a password is specified, FTP protocol is used, or, if the flag is set, TFTP protocol is used.
Use the following command sequence on the host to re-make the BSP boot ROM:cd target/config/mv260x make clean make bootrom.bin cp bootrom.bin /tftpboot/boot.binPower down the board and switch the ROM jumper to select socketed FLASH. Connect the Ethernet and console serial port cables, then power the board back up.
At the PPC1-Bug prompt, set up the network transfer from a TFTP host using niot. Important: You must have a TFTP server running on your host's subnet for the niop command to succeed. Using niot, the Client IP Address, Server IP Address, and Gateway IP Address must be set up for the user's specific environment:
PPC1-Bug>niot Controller LUN =00? Device LUN =00? Node Control Memory Address =00FA0000? Client IP Address =123.123.10.100? 123.321.12.123 Server IP Address =123.123.18.105? 123.321.21.100 Subnet IP Address Mask =255.255.255.0? Broadcast IP Address =255.255.255.255? Gateway IP Address =123.123.10.254? 123.321.12.254 Boot File Name ("NULL" for None) =? . Update Non-Volatile RAM (Y/N)? y PPC1-Bug>The file is transferred from the TFTP host to the target board using the niop command. The file name must be set to the location of the binary file on the TFTP host. The binary file must be stored in the directory identified for TFTP accesses, but the file name is a relative path and does not include the /tftpboot directory name:
PPC1-Bug>niop Controller LUN =00? Device LUN =00? Get/Put =G? File Name =? boot.bin Memory Address =00004000? Length =00000000? Byte Offset =00000000? PPC1-Bug>After the file is loaded onto the target, the pflash command is used to put it into soldered FLASH parts.
PPC1-Bug>pflash 4000:100000 ff000100When the command is finished, power down the board and switch the ROM jumper to select soldered FLASH. Then power the board back up.
From the "ok" prompt on the console, use the load command to get the image into RAM. You must have a TFTP server running on your host's subnet for the load command to succeed. The command takes the following form:
load /pci/ethernet@e:<host IP>,<file path/name>,<target IP>[,<gateway IP>]
The modifiable parameter load-base is set to the load-address of a binary image to be loaded. The factory preset value is 0x400000.For example, load-base must be modified to allow for the reserved 0x100 bytes at the beginning of a VxWorks boot image:
ok load-base h# 100 + to load-base ok load /pci/ethernet@e:144.191.1.8,boot.bin,144.191.1.7 Boot device: /pci/ethernet@e:144.191.1.8,boot.bin,144.191.1.7 File and args: ok load-base h# 100 - to load-baseFrom the "ok" prompt, determine the starting memory address of soldered FLASH:
ok 50 fal-l@ fef80050 ff0b0006 ^^^Use the indicated first three nibbles followed by five zeros as the start address. In this example, the start address is ff000000. (Note: "58 fal-l@" would return the socketed FLASH start address.)From the "ok" prompt, use the gflash command to program the image into FLASH. The command takes the following form:
<start addr> <size> <flash start addr> (gflash)To load the boot image into soldered FLASH, modify load-base as follows:
ok load-base 100000 ff000000 (gflash) Erasing ... Programming ... Verifying .... okPower down the board and switch the ROM jumper to select soldered FLASH. Then power the board back up.
This section describes miscellaneous information concerning this BSP and its use.
The config.h macro "INCLUDE_ECC" is disabled by default. If the Motorola PPC1 Debugger/Diagnostics monitor ROM program reports the following when starting:
"System Memory: 32MB, ECC NOT Enabled (Non-ECC-Memory Detected)"
Then you may not enable INCLUDE_ECC in config.h for your board, else it will fail to boot.
The delivered objects are: bootrom_uncmp, vxWorks, vxWorks.sym, and vxWorks.st.
The make targets are listed as the names of object-format files. Append .hex to each to derive a hex-format file name.
bootrom bootrom_uncmp bootrom_res_high (bootrom_res does not build) vxWorks (with vxWorks.sym) vxWorks_rom vxWorks.st vxWorks.st_rom vxWorks.res_rom_res_low (vxWorks.res_rom does not build) vxWorks.res_rom_nosym_res_low (vxWorks.res_rom_nosym does not build)
For these boards, the value of the CPU clock speed is read from the CPU configuration register using the macro MEMORY_BUS_SPEED which is defined in mv2600.h. For example:
clkFreqMhz = MEMORY_BUS_SPEED;
The Motorola Raven chip has a flaw which ignores PCI bus LOCK signals during access of local memory from the PCI bus. A new chip (Raven 3) is forthcoming from Motorola and addresses this flaw.Contact a Motorola representative for details on the new chips.
The diagram below shows flash EEPROM locations and jumpers relevant to VxWorks configuration:
___________________________________________________________________________ | MTX60x | | J37 (ROM ctrl) -> D | | | | | | | | | | | | ---- | | ==== | | ==== <== VxWorks Boot Flash | | ==== (soldered) | | ---- | | | | | | +----+ +----+ | | PPC1-Bug ==> X | | X | | | | U | | U | | | | 2 +----+ 1 +----+ | | | | COM 1 10/100 BaseT | |______--------_________________--------___________________________________|Key:
X vertical jumper installed
: vertical jumper absent
- horizontal jumper installed
" horizontal jumper absent
0 switch off
1 switch on
U three-pin vertical jumper, upper jumper installed
D three-pin vertical jumper, lower jumper installed
L three-pin horizontal jumper, left jumper installed
R three-pin horizontal jumper, right jumper installed
Tornado User's Guide: Getting Started, VxWorks Programmer's Guide: Configuration
Motorola MTX Series Single Board Computer Programmer's Reference Guide, Motorola PowerPC 603 RISC Microprocessor User's Manual, Motorola PowerPC 604 RISC Microprocessor User's Manual, Motorola PowerPC Microprocessor Family: The Programming Environments, Motorola MPC2604GA Integrated Secondary Cache for PowerPC Microprocessors (Glance) Data Sheets, Cirrus Logic Alpine VGA Family - CL-GD543X/4X Technical Reference Manual, DECchip 21140 PCI Fast Ethernet LAN Controller Hardware Reference Manual, National Semiconductor PC87308VUL (Super I/O Enhanced Sidewinder Lite) PC Controller Manual, SGS-Thompson MK48T59/559 CMOS 8K x 8 TIMEKEEPER SRAM Data Sheet, SYM53Cxx (was NCR53C8xx) Family PCI-SCSI I/O Processors Programming Guide, Zilog SCC (Serial Communications Controller) User's Manual, Zilog ZCIO Counter/Timer and Parallel I/O Unit User's Manual, Winbond W83C553 Enhanced System I/O Controller with PCI Arbiter Data Book, IEEE P1386 Draft 2.0 - Common Mezzanine Card Specification (CMC), IEEE P1386.1 Draft 2.0 - PCI Mezzanine Card Specification (PMC), IEEE Standard 1284 Bidirectional Parallel Port Interface Specification, Peripheral Component Interconnect (PCI) Local Bus Specification, Rev 2.1, PCI to PCI Bridge Architecture Specification 2.0, ANSI X3.131.1990 Small Computer System Interface-2 (SCSI-2) Draft Document