VxWorks BSP Reference : mcpn765
mcpn765 - Motorola MCPN765
This reference entry provides board-specific information necessary to run VxWorks. Before using a board with VxWorks, verify that the board runs in the factory configuration by using vendor-supplied ROMs and jumper settings and checking the RS-232 connection.
This BSP encompasses only the MCPN765 single-board computer. The series part numbers are of the form:
Part Number Description MCPN765-1131 233 MHz PowerPC 750, 32MB ECC SDRAM, 1MB L2 cache MCPN765-1141 233 MHz PowerPC 750, 64MB ECC SDRAM, 1MB L2 cache MCPN765-1241 466 MHz PowerPC 750, 64MB ECC SDRAM, 1MB L2 cache MCPN765-1251 466 MHz PowerPC 750, 128MB ECC SDRAM, 1MB L2 cache MCPN765-1261 466 MHz PowerPC 750, 256MB ECC SDRAM, 1MB L2 cache MCPN765-1271 466 MHz PowerPC 750, 512MB ECC SDRAM, 1MB L2 cache MCPN765-5131 400 MHz MPC7400, 32MB ECC SDRAM, 2MB L2 cache MCPN765-5141 400 MHz MPC7400, 64MB ECC SDRAM, 2MB L2 cache MCPN765-5151 400 MHz MPC7400, 128MB ECC SDRAM, 2MB L2 cache MCPN765-5161 400 MHz MPC7400, 256MB ECC SDRAM, 2MB L2 cache MCPN765-5171 400 MHz MPC7400, 512MB ECC SDRAM, 2MB L2 cache MCPN765-7361 500 MHz MPC7410, 256MB ECC SDRAM, 2MB L2 cache MCPN765-7371 500 MHz MPC7410, 512MB ECC SDRAM, 2MB L2 cache
Related Products
Part Number Description TM-PIMC-0101 MCPN765 transition module/PIM carrier: RJ-45 Ethernet connector, two RJ-45 async serial port connectors, two headers for async serial ports, one CompactFlash socket, two PIM slots CFLASH-048 CompactFlash memory card, 48MB CFLASH-096 CompactFlash memory card, 96MB RAM500-006,-016 256MB ECC SDRAM expansion modules
- Processor Address and Data Bus Parity
- This BSP supports parity protection of the processor's address bus and data bus. This option is enabled by default. If parity protection is not desired, undefine INCLUDE_BPE in config.h, rebuild both the bootrom and kernel images and re-flash the bootroms.
- Memory ECC Protection
- This BSP supports ECC memory and configures the Hawk memory controller for ECC operation by default. If ECC protection is not desired, undefine INCLUDE_ECC in config.h, rebuild both the bootrom and kernel images and re-flash the bootroms.
To load VxWorks, and for more information, follow the instructions in the Tornado User's Guide: Getting Started.
- Preparing the MCPN765 for VxWorks
- The MCPN765 can operate in a multi-node configuration with a system controller, like an MCP750 or CPV5000, in a compart PCI chassis. It can also operate in stand-alone mode in a non-system controller slot in the chassis. The Jumper "stand-alone operating mode" should be removed in multi-node mode, and connected when used in stand-alone mode. Incorrect setting can cause hanging, constant reboot or other unpredictable behavior.
Some of the early revisions of the MCPN765 boards may contain faulty L2 cache SRAM parts. (SPR 62854) They boot fine under PPCBug, but fail to boot with a standard VxWorks ROM. Some observed behavior of this problem is hanging and sometimes corrupted brief output on the serial console. To verify this problem, boot the MCPN765 in PPCBug mode and note the console output that displays the L2Cache size. A board with this problem will show NONE for the L2Cache size. The work around is to change #define INCLUDE_CACHE_L2 to #undef INCLUDE_CACHE_L2 in config.h and rebuild the bootrom. Faulty boards should be returned to Motorola for repair.
In previous non-system cPCI boards, the 21554 non-transparent PCI-to-PCI bridge was configured for software initialization. To address a start-up timing issue under PPC6-Bug, the 21554 is configured for self-initialization as delivered from the factory. Before using the MCPN765 with the default VxWorks configuration, the 21554 must be configured for sofware initialization.
The 21554 initialization mode is controlled by bit 2 (LSB=0) of offset 0x31 in an I2C SROM attached to the 21554. The state of this bit can be altered from the PPCBUG command line using the I2C SROM byte editor as follows:
PPC-Bug>srom;d Device Address =$0000A000 (N/Y)? y Reading SROM into Local Buffer..... $00 (&000) 80? <return> $01 (&001) 00? <return> . . Continue to press <return> until byte 0x31 is reached. . $31 (&049) 00? 04 (or 00 for PPCBUG mode) $32 (&050) 00? . Update SROM (Y/N)? y Writing SROM from Local Buffer..... Verifying SROM with Local Buffer...The following symptoms are the result of attempted operation with the wrong 21554 initialization mode:
Env Symptom PPCBUG Everything appears normal, but a "ver" command from the cPCI Host (Mesquite) does not report the presence of a MCPN765. VxWorks A standard VxWorks bootrom may fail to boot without issuing any error. In some cases it might boot, but the mis-configured MCPN765 can consume all available PCI allocation space and prevent the proper configuration of other boards in the cPCI chassis. If in doubt, re-build the PCI Host BSP with INCLUDE_SHOW_ROUTINES defined and display the PCI header of the 21554 on the MCPN765 using the pciHeaderShow command at the debug console of the PCI Host. If BAR2 has a value greater than 4MB plus the value in BAR1 (BAR1 + 0x00400000), using a VxWorks MCPN765 BSP image with DEC2155X_US_IO_OR_MEM0_SIZE set to the default value of 0x0040000, the MCPN765 is most likely mis-configured.
The following subsections list all supported and unsupported features, as well as any feature interaction.
The following features of the MCPN765 board family are supported:
Feature Description Processors MPC750; Up to 100MHz bus clock (derived from PCI bus clock) or MPC7400; Up to 100MHz bus clock (derived from PCI bus clock) or MPC7410; Up to 100MHz bus clock (derived from PCI bus clock) FLASH 1MB socketed (16-bit wide) 16MB soldered (64-bit wide) DRAM 32 to 1GB ECC Static DRAM (SDRAM); auto-sized or fixed Onboard: 32 to 512MB ECC SDRAM Optional memory mezzanines: 1 or 2 banks of 32MB to 256MB for a total of 512MB optional SDRAM NVRAM 32KB (MK48T37V) Peripherals Four 16550C asynchronous serial ports COM1, COM2, COM3, and COM4; Primary ATA/EIDE port and Compact Flash; Two 10baseT/100baseTX Ethernet interfaces ISA Interface full 64KB memory and I/O space PCI Interface 32-bit address, 32-bit data; complies with PCI Local Bus Specification, Revision 2.1 Miscellaneous RESET switch (3-second hold required)
The following features of the MCPN765 board family are not supported:
Feature Description Hawk Watchdog Timers PCI Interface 64-bit data; The hardware will perform 64-bit transfers if requested by an external PCI-master device, but does not generate 64-bit transactions in normal operation. Miscellaneous ABORT switch RTC MK48T37V; only NVRAM portion is used Peripherals USB ports 1 and 2; ISA Interface ISA RTC. Hot Swap No software support for hot swap. Timers Watchdog timers.
- MPIC Spurious Interrupts
- A race condition can exist between PCI write posting and interrupt processing which can cause an MPIC spurious interrupt. The problem occurs when a device's interrupt service routine writes to clear the interrupt source and then returns to the interrupted code. When the PCI bus is very busy, the write takes a while to get onto the bus and reach the interrupting device. During this time, the device's interrupt will remain asserted. If the PowerPC reenables external interrupts before the PCI write has reached the interrupting device, the processor will see the interrupt still asserted and re-enter the MPIC interrupt routines.
When the MPIC handler reads the vector, the MPIC reports a spurious interrupt because the PCI write has generally completed by then and the device's interrupt has now been cleared.
- Spurious Interrupt Workaround
- Modify the driver to perform a read from the PCI device (after writing to the device to clear the interrupt) to ensure that the write has fully propagated. sysPciOutWordConfirm( ) will do this automatically. Note that sysPciOutWordConfirm( ) reads from the address written which may cause an undesirable side-effect depending on the design of the hardware. If it does, just add a read from any safe location on the device. The primary goal is force to the write out of the posting queues before proceeding.
This section details device drivers and board hardware elements.
The device drivers and libraries included with this BSP are:
The sl82565IntrCtl module implements the VIA VT82C586B PCI-to-ISA Bridge (PIB) driver. The module was developed originally for the Symphonic Laboratories SL82565 PIB which has been succeeded by the VIA device.
i8250Sio: Intel 8250 UART driver (serial port). HawkAuxClk: Motorola Hawk timer driver for auxiliary clock. hawkI2c: Hawk I2C support. HawkMpic: Motorola Hawk MPIC interrupt controller driver. hawkPhb: Motorola Hawk PCI bus bridge chip driver. hawkSmc: Motorola Hawk System Memory Controller. dec21x40End: 10baseT/100baseTX DEC 21x4x Ethernet driver. dec2155xCpci: DEC 2155x Non-Transparent PCI-to-PCI Bridge support. ppcDecTimer: PowerPC decrementer timer driver (system clock). sysCache: MPC750 (Arthur), MPC7400 (Max) and MPC7410 (Nitro) L2 Cache support. sysMotVpd: Vital Product Data Support. sysMotVpdUtil: Vital Product Data Utility routines. sl82565IntrCtl: PIB interrupt controller driver.
Compact Flash support is disabled by default. In order to use the optional Compact Flash support, simply change the #undef INCLUDE_ATA line to read #define INCLUDE_ATA in config.h.
This BSP contains support for the Dec2155x non-transparent PCI-to-PCI bridge. This device provides read/write access to and from the Compact PCI bus (cPCI).The following support is provided:
Up to 4 user configurable downstream cPCI to local PCI windows. Up to 2 user configurable upstream local PCI to cPCI windows. Support for in-bound "doorbell" interrupts. Support for cPCI backpanel interrupts. cPCI to local CPU address translation. Local CPU to cPCI address translation. Build-time validation of Dec2155x configuration parameters.
The PReP standard does not support 64-bit PCI addressing. Therefore, this BSP does not provide support for 64-bit addressing through the Dec2155x.
NOTE: There is a limitation when the cPCI to local PCI or cPCI to local CPU address translation routines are presented with a cPCI address which maps into a downstream window on the local board. The translation will succeed and return an address, but when that address is accessed, the Dec2155x will attempt to access one of its own downstream windows. `The transfer will fail because PCI devices cannot access themselves on the cPCI bus'. Depending on how error detection is configured, the result will be invalid data or a PCI Master Abort. Interrupt vectors are provided for the interrupts associated with Dec2155x Hot Swap Power State transitions, Intelligent I/O (I2O), and the Upstream Memory 2 Base Address Register but no other support for these features is provided.
During system startup, the Dec2155x must be configured and unlocked before the host enumerates the cPCI bus. To meet this timing requirement, the Dec2155x is configured by the vxWorks boot ROM image. If changes to the Dec2155x configuration are made, new boot ROMs are required in addition to a new kernel. For proper operation, the Dec2155x configuration in the Boot ROMs must match the configuration used by the kernel.
The Dec2155x places certain limitations on window sizes and translation values. This BSP adheres to those limitations and provides build-time parameter checking to help avoid misconfigurations. Modifications to the default Dec2155x configuration provided in this BSP must be made with care to avoid invalid configurations. Information on the default Dec2155x configuration provided by this BSP is presented in the next section and modification guidelines appear later in this file.
The default Dec2155x configuration supports a host processor and up to 7 cPCI peripheral boards. The following interoperability is supported:
Host access to MCPN765 CSR and the low 4MB of MCPN765 DRAM. MCPN765 access to the low 4MB of host DRAM. MCPN765 access to peer cPCI boards.
The BSP provides these features using the following Dec2155x configuration:
Primary CSR and Downstream Memory 0 BAR:
Size: 4MB Direction: In-Bound (cPCI to MCPN765) cPCI Adrs: Dynamic (assigned by host) Local PCI Adrs: PCI_SLV_MEM_BUS (0x80000000 by convention) Local CPU Adrs: PCI_SLV_MEM_LOCAL (0x00000000 by convention) Use: R/W access to CSR (low 4KB) and MCPN765 DRAM (above 4KB) Upstream I/O or Memory 0 BAR:
Size: 4MB Direction: Out-Bound (MCPN765 to cPCI) cPCI Adrs: CPCI_MSTR_MEM_BUS (0x80000000 by convention) Local PCI Adrs: Dynamic (assigned by MCPN765) Local CPU Adrs: Dynamic (based on local PCI adrs) Use: R/W access to host DRAM Upstream Memory 1 BAR:
The remaining Dec2155x Base Address Registers are not used by the BSP and are available for use by the application.
Size: 32MB Direction: Out-Bound (MCPN765 to cPCI) cPCI Adrs: Base cPCI address of the host's dynamic PCI configuration area (0x00000000 for the default system controller BSP) Local PCI Adrs: Dynamic (assigned by MCPN765) Local CPU Adrs: Dynamic (based on local PCI adrs) Use: R/W access to cPCI devices
Due to the dynamic nature of PCI address allocation, the locations of the upstream Dec2155x windows move as devices are added to the MCPN765 PCI bus. Since these windows map the cPCI space into the local MCPN765 PCI and CPU address spaces, their positions determine where the cPCI resources appear when viewed by the MCPN765 CPU. Likewise, the downstream windows move as cPCI devices are added and removed. The downstream windows are used to map the on-board PCI and DRAM resources into the cPCI address space for access by the host and other cPCI devices.To assist with address translation, two translation routines are provided by this BSP:
sysLocalToBusAdrs( ) Translates a local CPU address to an equivalent cPCI or local PCI memory or I/O address. sysBusToLocalAdrs( ) Translates a cPCI or local PCI memory or I/O space address to a local CPU equivalent address.
NOTE: The translations performed by sysLocalToBusAdrs( ) and sysBusToLocalAdrs( ) are not symmetrical if one of the endpoints is the Compact PCI bus. sysLocalToBusAdrs( ) translates by locating a downstream window which makes the local CPU address visible in the cPCI address space. sysBusToLocalAdrs( ) performs a similar operation by locating an upstream window which makes the cPCI address visible in the local CPU address space. Since the two sets of windows map different areas of the local address space, the translation is not reversible.
Due to dynamic PCI address allocation, the PCI address assigned to the Dec2155x CSR area cannot be known until runtime. To determine the assigned address, it is necessary to read the Secondary CSR memory BAR (or the Secondary CSR I/O BAR if I/O space is to be used).The following code fragment derives the CPU address of the Scratchpad 0 register using its PCI memory space address:
UINT32 bar; /* get the contents of the secondary CSR memory BAR (see note below) */ if (pciConfigInLong (0, DEC2155X_PCI_DEV_NUMBER, 0, DEC2155X_CFG_SEC_CSR_MEM_BAR, &bar) != OK) { return (ERROR); } /* calculate the local PCI address of the scratchpad 0 register */ bar += DEC2155X_CSR_SCRATCHPAD0; /* convert the result to the CPU equivalent address */ if (sysBusToLocalAdrs (PCI_SPACE_MEM_PRI, (char *)bar, (char **)&bar) != OK) { return (ERROR); } return (bar);Once the local CPU address is known, the cPCI address can be derived by adding the following code fragment before returning the result:
NOTE: Using the constant DEC2155X_PCI_DEV_NUMBER ensures that the on-board Dec2155x is read. If a search of the local PCI bus had been performed using the Dec2155x device ID, the returned Bus, Device and Function numbers may have corresponded to a Dec2155x part found on an installed PMC card.
if (sysLocalToBusAdrs (PCI_SPACE_MEM_SEC, (char *)bar, (char **)&bar) != OK) return (ERROR); else return (bar);
At start-up, all Dec2155x interrupt sources are masked and cleared. Before unmasking an interrupt, an application ISR service routine must be attached to the appropriate Dec2155x interrupt vector using intConnect( ). Multiple ISR service routines can be connected to each vector if required by the application. Once the handler is attached, the interrupt can be enabled and disabled by calling sysDec2155xIntEnable( ) or sysDec2155xIntDisable( ) as required. Interrupt vector definitions for the Dec2155x internal interrupt sources are defined in mcpn765.h.Unique interrupt vectors are provided for each of the 16 bits in the Dec2155x Secondary IRQ register. Bit 0 (LSB) corresponds to DEC2155X_DOORBELL0_INT_VEC with the remaining bits mapped in sequence. These doorbell interrupts can be used for host-to-MCPN765 or MCPN765-to-MCPN765 event notification. The Dec2155x interrupt handler clears these interrupts which simplifies the application ISR.
Individual interrupt vectors are also provided for Dec2155x Hot Swap Power State and I2O in-bound list events. The Dec2155x interrupt handler also clears these interrupts.
The 64 Upstream Memory 2 BAR Page Crossing interrupts are all presented on a single interrupt vector and the application ISR is responsible for clearing the bits serviced. Calls to sysDec2155xIntEnable( ) and sysDec2155xIntDisable( ) enable or disable all 64 interrupts.
The Dec2155x interrupt handler provides a default service routine for all unclaimed interrupt vectors, including the Upstream Memory 2 BAR Page Crossing interrupt. The default routine reports the event and clears the interrupt source.
The Dec2155x can generate cPCI backpanel interrupts using any of the bits in the Primary IRQ register if they have been un-masked by the host. The following code fragment generates a compact PCI backpanel interrupt by setting bit 15 (MSB) of the Primary IRQ register:
if (sysBusIntGen (DEC2155X_DOORBELL15_INT_LVL, DEC2155X_DOORBELL15_INT_VEC) != OK) return (ERROR);Note that the cPCI bus does not provide an interrupt vector to the host. The vector number passed to sysBusIntGen( ) simply identifies which bit in the register to set. It is the host's responsibility to locate the interrupt source and clear the interrupt.
Most BSP configuration values are taken from on-board Vital Product Data (VPD) and Serial Presence Detect (SPD) serial EEPROMs. If invalid VPD or SPD information is suspected or reported, defining NONFATAL_VPD_ERRORS, BYPASS_VPD and/or BYPASS_SPD in config.h may permit operation using default parameters. These build switches are intended for use during debug only as they hard-code non-optimized SDRAM timing and other VPD information. Since the SDRAM timing is configured by the Bootrom, changing the state of BYPASS_SPD requires rebuilding the Bootrom image and re-flashing.
PCI_MSTR_IO_SIZE, PCI_MSTR_MEMIO_SIZE and PCI_MSTR_MEM_SIZE control the sizes of the available PCI address spaces. The windows defined by these parameters must be large enough to accommodate all of the PCI memory and I/O space requests found during PCI autoconfiguration. If they are not, some devices will not be autoconfigured.
By default, the companion system controller BSP allocates a 32MB area aligned to a 32MB boundary for dynamic PCI configuration. To access peer MCPN765 DRAM areas, an upstream window must be opened which matches the size of the host's dynamic PCI configuration area. For translation to work correctly, the host's dynamic PCI configuration area must be aligned to a multiple of the area's size and the corresponding Dec2155x upstream translation register must contain the area's base cPCI address (not CPU address). Since this BSP supports peer-to-peer access between MCPN765 DRAM areas, the default dynamic PCI configuration area for the MCPN765 is 64MB aligned to a 64MB boundary which satisfies these requirements.
NOTE: PCI auto-configuration is performed by the bootroms. Any changes to PCI_MSTR_IO_SIZE, PCI_MSTR_MEMIO_SIZE or PCI_MSTR_MEM_SIZE requires the creation of a new bootrom image. In addition to the peer access window, sufficient space must also be available for mapping the host DRAM upstream window and any space required by MCPN765-resident PCI devices. A margin must also be allowed for areas that are unusable due to window alignment requirements.
If the application does not require peer-to-peer MCPN765 DRAM access, the large 32MB window used to contain the host's dynamic PCI configuration area can be eliminated with a corresponding decrease in the required MCPN765 dynamic PCI configuration area. If peer-to-peer doorbell interrupts are still required, the doorbell interrupt registers of peer MCPN765 boards may be accessed through an I/O window which has much smaller CPU address space requirements. This would require re-configuring the default BSP to access host DRAM through Upstream Memory 1 BAR and using the Upstream I/O or Memory 0 BAR to access the peer MCPN765 doorbell interrupt registers.
Altering the Dec2155x configuration requires the careful consideration of several items:
Dec2155x window sizes and alignment. Dec2155x translation values. The size and alignment of the host's dynamic PCI configuration area. The size and alignment of the MCPN765's dynamic PCI configuration area.
The Dec2155x window parameters are controlled by #defines in config.h. There are three defines associated with each window:
..._SIZE determines the size of the window in bytes and must be an integral power of two. The minimum size for a PCI I/O space window is 64 bytes. The minimum size for a PCI memory space window is 4KB. To disable a window, set the size to 0. Note that the Dec2155x will not allow the Primary CSR and Downstream Memory 0 BAR to be disabled. If the size of this window is set to zero, the Dec2155x will default to a 4KB window. NOTE: If a window value is not a power of 2, or is below the minimum size, sysLib.c will not compile.
..._TYPE determines the type of the window and any placement restrictions. For proper operation, the window must be configured for placement anywhere in the 32-bit PCI address space. The default window sizes can be reduced without altering the sizes of the dynamic PCI configuration area. However, if the required values are significantly reduced from the default values, reducing the size of the dynamic PCI configuration area reduces the size of the MMU page tables at the ratio of 128:1 (a 128KB reduction saves 1KB of MMU table space).
..._TRANS determines the base address of the window on the target PCI bus. It is important to remember that this is a local PCI address (downstream window) or a cPCI address (upstream window). The translation value chosen must be an even multiple of the window size. NOTE: If the translation value is not a multiple of the window size, sysLib.c will not build.
The MCPN765 BSP supports shared memory backplane communication with the system controller as the Compact PCI host node. The Wind River documentation provides a great deal of information regarding shared memory concepts. The section below provides tutorial style information regarding the setup of a shared memory system involving the MCPN765 and a system controller.
Setting up a working shared memory system involves proper setting of certain "config.h" parameters and proper setting of boot parameters via the "c" command from the boot prompt. There are three components involved in shared memory communication which must be configured properly to create a working system:
The following restrictions apply to shared memory configurations.
- Anchor:
- This is an area of memory which must be accessible to all nodes participating in shared memory backplane communication. The anchor points to the actual shared memory buffer pool which must be located in the same memory space as the anchor itself. The associated "config.h" parameter is SM_ANCHOR_ADRS. In certain configurations, nonzero nodes will "poll" for the location of the anchor. "config.h" defines which comes into play for polling are SM_OFF_BOARD and SYS_SM_SYSTEM_MEM_POLL.
- Master node:
- This node is always designated as node zero. It is the node which sets up the anchor and shared memory pool. Once the anchor and shared memory pool is set up, the master node acts as a peer with the other nodes. The node number (0 in this case) is one of the boot parameters which can be set up with the "c" command from the bootline prompt.
- Sequential addressing:
- This is is governed by a "config.h" parameter, INCLUDE_SM_SEQ_ADDR and is used when sequential IP addresses are assigned to the participating nodes. Node zero is assigned the lowest IP address, followed by nodes 1, 2 etc. which are assigned the subsequent and sequential IP addresses. The advantage of sequential addressing is that fewer boot parameters must be specified to configure the system.
1) Node zero must not boot over the shared memory interface. Only nonzero nodes are allowed to boot over the shared memory "sm" interface. 2) The location of the anchor must be statically determinable by the master node (node 0). That is, the location of the anchor must either be a build-time static parameter or it must be able to be communicated to the master node via the "sm=xxxxxxxx" boot configuration parameter. The nonzero nodes need not know the location of the anchor at build or boot time but can be configured to poll for the anchor dynamically. Below are the crucial "config.h" parameters involved in shared memory:
NOTE: Another piece of shared memory terminology is "host node". The "host node" is the node which configures the compact PCI bus during startup initialization. In a system consisting of an system controller and one or more MCPN765 boards, the "host node" is the system controller. Don't confuse "host node" with "master node". "Master node" is simply a synonym for "node 0". The "host node" may or may not be the "master node". Note also that the "host node" need not necessarily be a VxWorks node.
Consider a system consisting of a system controller (host node) and two MCPN765 boards. The following six configurations are the only ones possible:
- CPCI_MSTR_MEM_BUS (address):
- The parameter is used to identify the address where the system DRAM will be configured at. This is dependent on the host board used and is defined in "config.h". The explaination says to set the value to 0x80000000 for a PowerPC system controller host (default) or 0x00000000 for a x86 host.
- SM_OFF_BOARD (TRUE or FALSE):
- The parameter has a configurable value of either TRUE or FALSE and directly determines the value of SM_ANCHOR_ADRS (the anchor address).
If SM_OFF_BOARD is defined as FALSE, then the anchor is on-board and SM_ANCHOR_ADRS is defined to be LOCAL_MEM_LOCAL_ADRS + SM_ANCHOR_OFFSET. LOCAL_MEM_LOCAL_ADRS is defined as 0x0 in "config.h" and SM_ANCHOR_OFFSET is defined as 0x4100 in "config.h" to work with an system controller. SM_ANCHOR_OFFSET needs to be changed to 0x1100 in "config.h" to work with a x86 system controller.
If defined as TRUE, then SM_ANCHOR_ADRS is defined as a function call: sysSmAnchorAdrs( ) (defined in "sysLib.c"). This function will dynamically poll, at system startup, various locations (explained below) for the exact location of the shared memory anchor.
Note that if "sm=xxxxxxxx" is used as a boot parameter, then SM_OFF_BOARD has no effect. The value of "xxxxxxxx" will be used as the anchor location regardless of the setting of SM_OFF_BOARD. If simply "sm" is used as a boot parameter, then SM_OFF_BOARD is queried at initialization time to determine if polling is required or not.
- SYS_SM_SYSTEM_MEM_POLL (#define or #undef):
- This define only has an effect if anchor polling is called for (because SM_OFF_BOARD is defined as TRUE and "sm" is used with no "=xxxxxxxx"). In this case, simply defining SYS_SM_SYSTEM_MEM_POLL will cause the node to poll for the anchor at compact PCI bus address CPCI_MSTR_MEM_BUS + SM_ANCHOR_OFFSET (0x80004100). "System memory" (which is the host node's DRAM) will be included as one of the locations where the anchor might reside. Note that other locations may be polled as well (explained later).
Not defining SYS_SM_SYSTEM_MEM_POLL will prevent the polling of system memory for the anchor.
- SYS_SM_ANCHOR_POLL_LIST (#define or #undef):
- This define has an effect only if polling is called for (see SM_OFF_BOARD explained above). When defined, SYS_SM_ANCHOR_POLL_LIST allows a list of devices, identified by device/vendor ID and subsystem ID/subsystem vendor ID to be specified as candidates for the anchor location. Devices which appear directly on the compact PCI bus are found and if they appear on the list defined by SYS_SM_ANCHOR_POLL_LIST, they are checked to see if they house the shared memory anchor. The memory defined by the first memory BAR is queried at offset SM_ANCHOR_OFFSET (0x4100 by default, defined in "config.h"). If SYS_SM_ANCHOR_POLL_LIST is not defined, ALL devices on the compact PCI bus will be considered candidates for the anchor location and will be polled. If SYS_SM_ANCHOR_POLL_LIST defined but empty, NO devices on the compact PCI bus will be considered candidates for the anchor location. In that case, the only location polled would be system memory if SYS_SM_SYSTEM_MEM_POLL (see above) was defined.
- INCLUDE_SM_SEQ_ADDR (#define or #undef)
- If "undef'ed", sequential addressing is disabled. This symbol is defined by default.
Master node on... Anchor on... Sequential Addressing? 1. System Controller System Controller NO 2. System Controller System Controller YES 3. MCPN765 System Controller NO 4. MCPN765 System Controller YES 5. MCPN765 MCPN765 NO 6. MCPN765 MCPN765 YES
Master node on MCPN765 and Anchor on an x86 system controller is not supported.
Below is a description of how each of the above systems would be configured. Crucial "config.h" and boot parameter settings for an example system are given. In each example, SYS_SM_ANCHOR_POLL_LIST was defined to contain information identifying the Dec2155x bridge chip (present on the MCPN765 board). See "config.h" for the example of how this was done.
1) System Controller master, System Controller anchor, no sequential addressing: System Controller: #define SM_OFF_BOARD FALSE #undef SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : dc host name : sunray processor number : 0 inet on ethernet (e) : 124.170.16.112 inet on backplane (b): 124.200.200.1:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : gamma MCPN765-1: #define SM_OFF_BOARD TRUE #define SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : sm host name : sunray processor number : 1 inet on ethernet (e) : 124.170.16.109 inet on backplane (b): 124.200.200.2 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.1 target name (tn) : alpha MCPN765-2: (same "config.h" setup as MCPN765-1 above) boot device : sm host name : sunray processor number : 2 inet on ethernet (e) : 124.170.16.110 inet on backplane (b): 124.200.200.3 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.1 target name (tn) : beta
2) System Controller master, System Controller anchor, sequential addressing: System Controller: #define SM_OFF_BOARD FALSE #define SYS_SM_CPCI_BUS_NUMBER 1 #undef SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : dc host name : sunray processor number : 0 inet on ethernet (e) : 124.170.16.112:ffffff00 inet on backplane (b): 124.200.200.1:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : gamma MCPN765-1: #define SM_OFF_BOARD TRUE #define SYS_SM_CPCI_BUS_NUMBER 1 #define SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : sm host name : sunray processor number : 1 inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : target name (tn) : alpha MCPN765-2: (same "config.h" setup as MCPN765-1 above) boot device : sm host name : sunray processor number : 2 inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : target name (tn) : beta
3) MCPN765 master, System Controller anchor, no sequential addressing: System Controller: #define SM_OFF_BOARD TRUE #undef SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : sm host name : sunray processor number : 1 inet on ethernet (e) : 124.170.16.112 inet on backplane (b): 124.200.200.1 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.2 target name (tn) : gamma MCPN765-1: #define SM_OFF_BOARD FALSE #define SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : dc processor number : 0 host name : sunray inet on ethernet (e) : 124.170.16.109 inet on backplane (b): 124.200.200.2:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : alpha MCPN765-2: #define SM_OFF_BOARD TRUE #define SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : sm processor number : 2 host name : sunray inet on ethernet (e) : 124.170.16.110 inet on backplane (b): 124.200.200.3 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.2 target name (tn) : beta
4) MCPN765 master, System Controller anchor, sequential addressing: System Controller: #define SM_OFF_BOARD TRUE #undef SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : sm processor number : 1 host name : sunray inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : target name (tn) : gamma MCPN765-1: #define SM_OFF_BOARD FALSE #define SYS_SM_CPCI_BUS_NUMBER 1 #define SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : dc processor number : 0 host name : sunray inet on ethernet (e) : 124.170.16.109:ffffff00 inet on backplane (b): 124.200.200.1:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : alpha MCPN765-2: #define SM_OFF_BOARD TRUE #define SYS_SM_CPCI_BUS_NUMBER 1 #define SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : sm processor number : 2 host name : sunray inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : target name (tn) : beta
5) MCPN765 master, MCPN765 anchor, no sequential addressing: System Controller: #define SM_OFF_BOARD TRUE #undef SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : sm processor number : 1 host name : sunray inet on ethernet (e) : 124.170.16.112 inet on backplane (b): 124.200.200.1 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.2 user (u) : ball ftp password (pw) (blank = use rsh): flags (f) : 0x0 target name (tn) : gamma MCPN765-1: #define SM_OFF_BOARD FALSE #undef SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : dc processor number : 0 host name : sunray inet on ethernet (e) : 124.170.16.109 inet on backplane (b): 124.200.200.2:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : alpha MCPN765-2: #define SM_OFF_BOARD TRUE #undef SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : sm processor number : 2 host name : sunray inet on ethernet (e) : 124.170.16.110 inet on backplane (b): 124.200.200.3 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.2 target name (tn) : beta
6) MCPN765 master, MCPN765 anchor, sequential addressing: System Controller: #define SM_OFF_BOARD TRUE #undef SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : sm processor number : 1 host name : sunray inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : target name (tn) : gamma MCPN765-1: #define SM_OFF_BOARD FALSE #undef SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : dc processor number : 0 host name : sunray inet on ethernet (e) : 124.170.16.109:ffffff00 inet on backplane (b): 124.200.200.1:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : alpha MCPN765-2: #define SM_OFF_BOARD TRUE #undef SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : sm processor number : 2 host name : sunray inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : flags (f) : 0x0 target name (tn) : beta
On-board RAM for these boards always appears at address 0x00000000 locally.Dynamic memory sizing is supported. By default, LOCAL_MEM_AUTOSIZE is defined so memory is auto-sized at hardware initialization time. If auto-sizing is not selected, LOCAL_MEM_SIZE must be set to the actual size of DRAM memory available on the board to ensure all memory is available. The default fixed RAM size is set to 32MB (see LOCAL_MEM_SIZE in config.h).
Note that LOCAL_MEM_SIZE only controls the amount of memory mapped by the MMU. It does not control the amount of memory detected and configured by the Bootrom.
The amount of physical memory indicated by the Serial Presence Detect data determines the Hawk memory controller configuration and, if enabled, the ECC initializaton range. If hardware memory problem is suspected, the Bootrom can be configured to ignore the Serial Presence Detect data and program the Hawk memory controller with a set of default parameters. For more information on this feature, see the BYPASS_SPD note in config.h.
The system interrupt vector table has 256 entries. Vectors for the various devices on the buses are assigned hierarchically as follows:
The specific ISA vector number assignments are:
Vector# Assigned to 00 - 0f [User defined] 10 - 1f All MPIC interrupts 20 - 23 Hawk timers 24 - 27 Hawk interprocessor dispatch 28 Hawk detected internal errors 29 - 5f [User defined] 60 - 72 Dec2155x interrupts 73 - ff [User defined]
Vector numbers not in the table are not used by this BSP.
Vector# Assigned to 02 [Cascade interrupt from PIC2] 03 COM2 and COM4 04 COM1 and COM3 05 Dec21554 Secondary Interrupt 08 Abort Switch/RTC [Not Used] 09 Hawk WDT1/2 [Not Used] 10 Ethernet 1 11 Internal USB [Not Used] 12 Ethernet 2 14 Primary IDE Interface 15 PMC1 and PMC2 Interrupt The standard ISA Intel 8259 Programmable Interrupt Controllers (PICs) assert their interrupts through the Raven MPIC as an external interrupt. The external interrupt vector numbers (MPIC vectors) are:
Vector numbers not in the table are not used by this BSP.
Vector# Assigned to 0x10 PBC (8259) 0x11 TL16C550 UART 0x12 PCI Ethernet 1 0x13 Hawk WDT1/2 [Not Used] 0x14 Dec21554 0x15 CompactPCI Bus1 INTA# [Not Used] 0x16 CompactPCI Bus1 INTB# [Not Used] 0x17 CompactPCI Bus1 INTC# [Not Used] 0x18 CompactPCI Bus1 INTD# [Not Used] 0x19 PMC1 INTA#/PMC2 INTB# 0x1a PMC1 INTB#/PMC2 INTC# 0x1b PMC1 INTC#/PMC2 INTD# 0x1c PMC1 INTD#/PMC2 INTA# 0x1d PCI-Ethernet 2 0x1e Abort [Not Used] 0x1f RTC - Alarm [Not used] The Hawk Multi-Processor Interrupt Controller (MPIC) sets system interrupt priorities and serves as controller of all external interrupts. Each of its 16 interrupt control registers, designated IRQ0 through IRQ15, can be programmed with a relative priority from 15, the highest, to 0, the lowest. A priority of zero effectively disables the interrupt. The IRQ number and priority assignments are as follows:
For further details, refer to the appropriate board's reference guide.
Hawk MPIC IRQ Priority IRQ Source IRQ0 9 PBC (8259) IRQ1 8 TL16C550 UART IRQ2 14 PCI Ethernet 1 IRQ3 0 Hawk WDT1/2 [Not Used] IRQ4 10 Dec21554 IRQ5 0 CompactPCI Bus1 INTA# [Not Used] IRQ6 0 CompactPCI Bus1 INTB# [Not Used] IRQ7 0 CompactPCI Bus1 INTC# [Not Used] IRQ8 0 CompactPCI Bus1 INTD# [Not Used] IRQ9 3 PMC1 INTA#/PMC2 INTB# IRQ10 3 PMC1 INTB#/PMC2 INTC# IRQ11 3 PMC1 INTC#/PMC2 INTD# IRQ12 3 PMC1 INTD#/PMC2 INTA# IRQ13 13 PCI Ethernet 2 IRQ14 0 Abort [Not Used] IRQ15 0 RTC - Alarm [Not used] There are only four PCI bus interrupts: A, B, C, and D. They are shared among all PCI bus devices and do not have levels. PCI bus interrupts are wired directly to the MPIC and, therefore, have preassigned system vector numbers and interrupt levels.
To simplify the addition of PCI-based add-in cards, the BSP provides a PCI auto-configuration library. When INCLUDE_AUTOCONF is defined (default), the BSP will automatically locate and configure installed PCI devices. When INCLUDE_AUTOCONF is not defined (intended for debug use only), add-in PCI devices will not be located or configured.When PCI auto-configuration is selected, the auto-cofiguration library will be called from sysHwInit to discover and configure the installed PCI devices and bridges. Device configuration includes the following PCI information:
- Base Address Registers (BARs)
- Space in the address map is dynamically allocated to each valid BAR detected. Allocation pools are maintained for the following PCI address spaces:
16-Bit PCI I/O
32-Bit PCI I/O
PCI Memory I/O (non-prefetchable memory)
PCI Memory (pre-fetchable)
- Interrupt Routing
- The correct interrupt vector number is placed in the intLine register of the device's PCI header. To connect to the devices's interrupt, simply call intConnect with the value read from intLine.
- PCI Header Completion
- The PCI auto-configuration library fills in the remainder of the PCI header as follows:
Cache Line Size = _CACHE_ALIGN_SIZE/4
Latency Timer = PCI_LAT_TIMER
Command Register = I/O enabled, Memory enabled and Bus Master enabled.
- Transparent PCI-to-PCI Bridge Configuration
- Transparent PCI-to-PCI bridges encountered during PCI auto-configuration will be configured as necessary and devices detected behind the bridge will be configured as described above. Bridge configuration consists of the following:
Primary Bus Number, Secondary Bus Number and Subordinate Bus Number are filled in according to the bridge's position in the system.
I/O Base and Limit registers are configured as required to forward PCI transactions to PCI devices detected and configured beyond the bridge.
Memory Base and Memory Limit registers are configured as required to forward PCI transactions to PCI devices detected and configured beyond the bridge.
Command Register = I/O enabled, Memory enabled and Bus Master enabled.
Cache Line Size = _CACHE_ALIGN_SIZE/4
Primary Latency Timer = PCI_LAT_TIMER
Secondary Latency Timer = PCI_LAT_TIMER
The 32-bit PCI bus is fully supported under the PCI Local Bus Specification, Revision 2.1. The 64-bit extensions are not supported. All configuration space accesses are made with BDF (bus number, device number, function number) format calls in the pciConfigLib module. For more information, refer to the reference entries. mcpn765_xxpciXxx.
The four debug ports on the MCPN765 board family are implemented in a TLC16550 UART. The RJ-45 jack is placed on the front panel of the MCPN765 board and is configured as a DTE connection.By default, the serial port is configured as asynchronous, 9600 baud, with 1 start bit, 8 data bits, 1 stop bit, no parity, and no hardware or software handshake. Hardware handshake using RTS/CTS is a supported option. If an optional transition module is used, the front serial console port can be routed to the port on the transition module by configuring jumper J11 on the transition module.
SCSI is not available on the MCPN765 board family.
The MCPN765 has two Ethernet ports which are 10baseT and 100baseTX compatible using a RJ45 jack on the front or rear panels for connection to this facility.A "Secondary" dec21x40End Ethernet driver is not configured by default. To enable the "Secondary" Ethernet driver and supporting End interfaces, define INCLUDE_SECONDARY_ENET in config.h. The "Primary" Ethernet device, by default, is the front panel Ethernet device found at PCI DEVSEL 14. The "Secondary" Ethernet device is the rear panel Ethernet device found at PCI DEVSEL 19. If a different configuration is required, change PCI_IDSEL_PRI_LAN and PCI_IDSEL_SEC_LAN in config.h.
The first ethernet interface is designated as dc0, while the second one as dc1. The second interface will be loaded into the END mux if INCLUDE_SECONDARY_ENET is defined. To attach the secondary interface as 123.4.5.67 with a class C mask, the following calls can be performed:
ipAttach (1, "dc");
ifMaskSet ("dc1", 0xffffff00);
ifAddrSet ("dc1", "123.4.5.67");The Media Access Control (Ethernet) address for each port is obtained from a serial ROM contained in the DEC21143 chip.
The Ethernet driver automatically senses and configures the port as 10baseT or 100baseTX. The Ethernet driver is compatible with both DEC2104x and DEC2114x devices (for the MCPN765 family, a DEC21143 chip is used).
If there is a special need to override Auto-Negotiation of the dec21x40End driver and the MII PHY, the flag DEC_USR_FLAGS_143 needs to be changed to reflect the connection type. The flags used to control the driver are:
Name Value Description DEC_USR_FORCE_MODE 0x01000000 Force PHY to user settings DEC_USR_FD 0x00400000 Force Full Duplex DEC_USR_100MB 0x02000000 Force 100 Mbps The following table summarizes the settings:
So, for example, if the user wishes to force the driver/PHY to 10Mbps/FD, the flag DEC_USR_FLAGS_143 (in sysDec21x40End.c) would be defined as:
DEC_USR_FORCE_MODE DEC_USR_FD DEC_USR_100MB Connection YES NO NO 10Mbps HD YES YES NO 10Mbps FD YES NO YES 100Mbps HD YES YES YES 100Mbps FD NO X X Auto-Negot. #define DEC_USR_FLAGS_143 (DEC_USR_21143 | DEC_USR_PHY_CHK |
DEC_USR_FORCE_MODE | DEC_USR_FD)
- Flash Memory
- The MCPN765 comes with four AMD AM29LV323C 32Mbit devices. They are soldered on the base board as 16MB of FLASH bank A memory. The default setup puts the VxWorks bootrom into this bank of FLASH memory. TrueFFS, an optional product of Tornado and VxWorks, can co-exists with the bootrom in the same FLASH bank in distinct blocks.
The file sysTffs.c in the BSP configures TrueFFS for this board. The flash driver amd29LvMtd.c, found in target/src/drv/tffs, contains the MTD for the AMD AM29LV323 and AM29LV160D flash parts.
- Building With TrueFFS
- To build the BSP with TrueFFS support from the command line, edit the BSP's config.h file to change #undef INCLUDE_TFFS to #define INCLUDE_TFFS. The following macros should also be added (assuming use of network loading):
#define INCLUDE_SHELL #define INCLUDE_NET_SYM_TBL #define INCLUDE_LOADERIf you use Tornado's project facility, the following should be done:Include "TrueFFS Flash File System" in your project which is located
at Hardware -> Peripherals in the project tree.Include "Initialize Symbol Table" in your project which is located
at Development Tool Components -> Symbol Table Components -> Symbol
Table Initialization Components in the project tree.Include "Shell Banner", "Target Debugging", and "Target Shell" in
your project which is located at Development Tool Components -> Target
Shell Components in the project tree.Rebuild the bootrom and the BSP by following the steps in the ROM section. Note that the bootrom needs to be re-programmed for the changes to take effect.
- Using TrueFFS
- After booting with the new bootrom, the bank A FLASH is mapped at address 0xF4000000 with 16MB of memory contained in 71 sectors. Sectors 0 through 3 (1 MB) are reserved for the bootrom, and sectors 4 through 70 can be used by TrueFFS. tffsRawio( ) can be used to perform a one time setup, using the syntax:
tffsRawio(drive_no, function_no, first_unit, number_of_units)For example, the following commands can be issued on the target shell. This will erase and format the FLASH for use by TrueFFS, and mount it as "/flash" device in VxWorks. The tffsRawio( ) and sysTffsFormat( ) commands may take up to ten minutes each to complete. Interrupting the board during this time risks corrupting the bootrom in the same flash device:
/* warning: data in flash will be lost! */ tffsRawio (0, 3, 4, 60); sysTffsFormat (); usrTffsConfig (0, 0, "/flash");You should now be able to use VxWorks I/O and dosFs commands to access the FLASH device as if it is a disk. Use devs and dosFsShow to examine the device. After rebooting, use only usrTffsConfig( ) to re-mount the FLASH device and previous changes to the file system should be preserved. For more information about the TrueFFS Flash File System, refer to the "TrueFFS for Tornado Programmer's Guide".
Errors encountered during the early stages of the bootrom execution are saved in the Hawk's general purpose registers as bit flags. Once the system is able to report these errors, they are logged in the following form:
Bootrom Error: Group = X, Code = 0xXXXXXXXXThe following errors are defined for this BSP:
Group Bit Pattern Meaning A 0x80000000 Unable to read bus frequency from VPD. A 0x40000000 Using default SDRAM Timing.
NOTE: When multiple errors are present simultaneuously, the error bits are OR'd together.
The supported boot devices are:sm - shared memory
dc - Ethernet (10baseT or 100baseTX)
The boot methods are affected by the boot parameters. If no password is specified, RSH (remote shell) protocol is used. If a password is specified, FTP protocol is used, or, if the flag is set, TFTP protocol is used.These protocols are used for both Ethernet and shared memory boot devices.
The following instructions will program the soldered flash (bank A) on the MCPN765 using the PPCBug software in the socketed flash (bank B).Use the following command sequence on the host to re-make the BSP boot ROM:
cd target/config/mcpn765 make clean make bootrom.bin chmod 666 bootrom.bin cp bootrom.bin /tftpbootMake sure the PPCBug software is optional from the socketed flash where the jumper J8 (flash back selector) is set across pins 2 and 3. Connect the ethernet and console serial port cables, then power up the board.
Using niot, the Client IP Address, Server IP Address, and Gateway IP Address must be set up for the user's specific environment:
PPC-Bug>niot Controller LUN =00? Device LUN =00? Node Control Memory Address =00FA0000? Client IP Address =123.123.10.100? 123.321.12.123 Server IP Address =123.123.18.105? 123.321.21.100 Subnet IP Address Mask =255.255.255.0? Broadcast IP Address =255.255.255.255? Gateway IP Address =123.123.10.254? 123.321.12.254 Boot File Name ("NULL" for None) =? . Update Non-Volatile RAM (Y/N)? y PPC-Bug>The file is transferred from the TFTP host to the target board using the niop command. Important: You must have a TFTP server running on your host's subnet for the niop command to succeed. The file name must be set to the location of the binary file on the TFTP host. The binary file must be stored in the directory identified for TFTP accesses, but the file name is a relative path and does not include the /tftpboot directory name:
PPC-Bug>niop Controller LUN =00? Device LUN =00? Get/Put =G? File Name =? bootrom.bin Memory Address =00004000? Length =00000000? Byte Offset =00000000? PPC-Bug>After the file is loaded onto the target, the pflash command is used to put it into soldered FLASH parts.Note that the MCPN765 can have varying sized soldered FLASH parts. The base address of ROM bank A is programmed by PPC-Bug depending on the size found in VPD. To determine the FLASH base address, dump the Hawk's ROM base A address register at 0xfef80050:
PPC-Bug>md 0xfef80000 FEF80000 10574803 00000000 00010200 00000000 .WH............. FEF80010 85850000 00000000 00080000 00000000 ................ PPC-Bug> FEF80020 63000000 00000000 00000001 00000000 c............... FEF80030 05290000 00000000 0FF210E0 00000000 .).............. PPC-Bug> FEF80040 00000000 00000000 00000000 00000000 ................ FEF80050 F40C0006 00000000 FF800006 00000000 ................ ^^^^^^^^The upper byte correlates to the destination address to be used in the pflash command below:
PPC-Bug>pflash 4000:fff00 f4000100When the command is finished, power down the board and switch the ROM jumper to select soldered FLASH. Then power the board back up.
This section describes miscellaneous information concerning this BSP and its use.
A requirement for this BSP to work is that the SROMs on the board must be programmed correctly. If they are incorrect or not programmed, the BSP will not run.
The delivered objects are: bootrom, vxWorks, vxWorks.sym, and vxWorks.st.
The make targets are listed as the names of object-format files. Append .hex to each to derive a hex-format file name, or .bin to each to derive a binary format file name.bootrom
bootrom_uncmp
bootrom_res_high
vxWorks (with vxWorks.sym)
vxWorks.st
vxWorks_rom
vxWorks.st_rom
vxWorks.res_rom_res_low (builds but does not execute)
vxWorks.res_rom_nosym_res_low (builds but does not execute)
The following table describes the address mapping created for the Extended PCI model from the CPU point of view. The basic intent is to allow as much PCI non-prefetchable (also known as PCI MemIO) and prefetchable memory (also known as PCI Mem) as possible. This is done by starting the location of PCI MemIO at the end of on board DRAM plus one. The maximum size of this window depends on the amount of on-board DRAM (the base) up to the hardware defined "Optional Flash Bank" location at 0xF4000000 (the top). The defaults are 64MB for non- prefetchable PCI memory and 32MB for prefetchable PCI memory. These values are user configurable by changing PCI_MSTR_MEMIO_SIZE and PCI_MSTR_MEM_SIZE in config.h. There is roughly 2.8GB available for PCI memory when 1GB of local DRAM is installed.
In order to use the optional pseudo-PReP mapping configuration, simply change the #define EXTENDED_PCI line to read #undef EXTENDED_PCI in config.h.
Start Size Access to 0x0 LOCAL_MEM_SIZE DRAM (32MB - 1GB) LOCAL_MEM_SIZE 64MB PCI MEM I/O space LOCAL_MEM_SIZE+64MB 32MB 32-bit PCI MEM space 0xF4000000 160MB Optional Flash Banks 0xFC000000 256KB MPIC Reg space 0xFC040000 0x02F40000 [Not used] 0xFD000000 16KB ISA Legacy I/O space 0xFD004000 64KB 16-bit PCI I/O space 0xFD010000 8MB 32-bit PCI I/O space 0xFEF80000 64K Hawk SMC Registers 0xFEF90000 384K Reserved 0xFEFF0000 64K Hawk PHB Registers 0xFF000000 8M ROM/FLASH Bank A 0xFF800000 1M ROM/FLASH Bank B 0xFF900000 6M Reserved 0xFFF00000 1M ROM/FLASH Bank A or Bank B
The following table describes the modified PowerPC Reference Platform (PReP) address maps created from the CPU point of view. Tornado-compatible mapping deviates only slightly from the model.
Start Size Access to 0x0 LOCAL_MEM_SIZE DRAM (32MB - 1GB) LOCAL_MEM_SIZE 0x80000000 - [Not used] LOCAL_MEM_SIZE 0x80000000 16KB Legacy ISA I/O space 0x80004000 48KB 16-bit PCI I/O space 0x80010000 8MB 32-bit PCI I/O space 0x80810000 0x3F7F0000 [Not Used] 0xC0000000 64MB PCI MEM I/O space 0xC4000000 8MB 32-bit PCI MEM space 0xC4800000 0x37800000 [Not Used] 0xFC000000 256KB MPIC Reg space 0xFC040000 0x02F40000 [Not used] 0xFEF80000 64K Hawk SMC Registers 0xFEF90000 384K Reserved 0xFEFF0000 64K Hawk PHB Registers 0xFF000000 8M ROM/FLASH Bank A 0xFF800000 1M ROM/FLASH Bank B 0xFF900000 6M Reserved 0xFFF00000 1M ROM/FLASH Bank A or Bank B
The pseudo-PReP mapping from the PCI bus point of view is:PCI I/O Space Access
Start Size Access to Controlled by 0x00000000 16KB ISA Legacy I/O space Fixed 0x00004000 48KB 16-bit PCI I/O Fixed 0x00010000 8MB 32-bit PCI I/O space PCI_MSTR_IO_SIZE PCI MEM Space Access
Start Size Access to Controlled by 0x00000000 64MB PCI MEM I/O PCI_MSTR_MEMIO_SIZE 0x04000000 8MB PCI MEM PCI_MSTR_MEM_SIZE 0x3C000000 256KB MPIC REGS Fixed 0x80000000 Varies DRAM space Auto-Sized or LOCAL_MEM_SIZE (32MB to 1GB)
The MCPN765 does not contain an on-board oscillator for generating the processor bus clock. The processor bus clock is generated using a PLL which multiplies the system PCI bus frequency up to create the CPU bus frequency. Since the system PCI bus frequency is not known in advance, the MCPN765 BSP calculates the CPU bus frequency using the 16550 baud rate clock as a reference. The calculated value (in Hertz) may be accessed using the macro MEMORY_BUS_SPEED which is defined in mcpn765.h.Note that the raw calculated value is returned and may not exactly agree with the expected nominal value. For example, 100 MHz may be returned as 99,999,744 (or 100,000,128) if that was the value calculated. Returning the raw value allows the user to determine the rounding on a case-by-case basis. For example, if the user requires a value rounded to the nearest MHz, the following code fragment could be used:
clkFreqMhz = (MEMORY_BUS_SPEED + 500000)/1000000;
Currently when the memory mezzanines are added, the Bus speed is slowed down from 100 MHz to 83.3 MHz. This consequently results in the processor speed being reduced as well. This release was tested in this configuration.Future revisions of the LoneStar based board will be modified so that when the bus speed is slowed down, the processor speed increases. Preliminary tests showed that this modification did not affect this release of the BSP.
It has been discovered that the VIA PCI-to-ISA bridge device has a subtractive decoder which cannot be disabled. Therefore, when a PCI access is performed to a non-existent PCI I/O or Memory address on the local PCI bus, the VIA PCI-to-ISA bridge will respond and forward the transaction onto the ISA bus using the lower 24 bits of the PCI address as the ISA address. The operation can result in spurious transactions if the resulting ISA address maps to a valid ISA device. If the ISA device does not exist, the PCI-to-ISA bridge returns 0xffffffff if the transaction is a read and discards the data on a write. This behavior prevents the generation of the Master Abort used to detect a faulty local PCI access and essentially nullifies the results of a probe directed at a local PCI I/O or Memory address. If the PCI transaction is claimed by the Dec2155x and forwarded to the cPCI bus, the PCI-to-ISA subtractive decoder does not respond and the Dec2155x will provide the proper response (Target Abort) when an invalid cPCI I/O or Memory address is presented. In this case, the results of the probe are valid. The probe result is also valid if the access references an address that produces an MMU fault regardless of the target address space (local or cPCI I/O or Memory or local DRAM).
The diagrams below show flash EEPROM locations and jumpers relevant to VxWorks configuration:
Serial port 1 (COM1) and the Ethernet port appear both on the MCPN765 and the transition modules, TM-PIMC-0001 and TM-PIMC-0101. The TM-PIMC-0001 provides connections for a PIM card, COM3 and COM4, and an IDE CompactFLASH socket. The TM-PIMC-0101 provides connections for two PMC I/O slots, two Ethernet ports, and a EIDE CompactFLASH connector. As noted in the MCPN765 Installation and Use manual, neither of the TM-PIMC-0001 nor TM-PIMC-0101 provide USB connections.
____________________________________________________________________________ | Interface to the TM-PIMC-0001 or | | TM-PIMC-0101 Transition Module | ____________________________________________________________________________ | | | =========== =========== =========== =========== | | | | =========== =========== =========== =========== | | PMC slot PMC slot | | | | D <-- J8 (ROM Ctrl) | | ========== | | Memory mezz | | | | | | | | | | | | | | | | | | | | +-----+ +-----+ | | |XU1 | |XU2 | | | | | | | | | +-----+ +-----+ | | | | | |______.......................___.......................____----_____----__| PCI Mezzanine Card PCI Mezzanine Card 10/100 Com1 Cutout Cutout base TKey:
U three-pin vertical jumper, upper jumper installed
D three-pin vertical jumper, lower jumper installed
L three-pin horizontal jumper, left jumper installed
R three-pin horizontal jumper, right jumper installed
Tornado User's Guide: Getting Started, VxWorks Programmer's Guide: Configuration
Motorola MCPN765 Installation and Use Guide, Motorola MCPN765 Programmer's Reference Guide, Motorola Computer Group Online Documentation, http://library.mcg.mot.com/mcg/boards Motorola PowerPC 750 RISC Microprocessor User's Manual, Motorola PowerPC 7400 RISC Microprocessor User's Manual, Motorola PowerPC 7410 RISC Microprocessor User's Manual, Motorola PowerPC Microprocessor Family: The Programming Environments, Texas Instruments TL16C550C Asynchronous Communications Element Data Sheet, VT82C586B PCI Peripheral Bus Controller, DECchip 21143 PCI Fast Ethernet LAN Controller Hardware Reference Manual, IEEE P1386.1 Draft 2.0 - PCI Mezzanine Card Specification (PMC), IEEE P1386 Draft 2.0 - Common Mezzanine Card Specification (CMC), Peripheral Component Interconnect (PCI) Local Bus Specification, Rev 2.1, PCI to PCI Bridge Architecture Specification 2.0, PICMG 2.0 D2.14 CompactPCI Specification, Digital Semiconductor 2155x PCI-to-PCI Bridge for Embedded Applications Hardware Reference Manual,