VxWorks BSP Reference : mcpn750

MCPN750

NAME

MCPN750 - Motorola PowerPlus

INTRODUCTION

This reference entry provides board-specific information necessary to run VxWorks. Before using a board with VxWorks, verify that the board runs in the factory configuration by using vendor-supplied ROMs and jumper settings and checking the RS-232 connection.

The Motorola CompactPCI series of boards includes the following families: MCP750 and MCPN750. This BSP encompasses MCPN750 only.

The MCPN750 single-board computer is based on the PowerPC MPC750 (Arthur) microprocessors. The series part numbers are of the form:

    MCPN750-nnnn

    where
        nnnn = Processor speed and ECC DRAM size (DRAM contained on-board)
            1222 = 266 MHz w/16MB
            1232 = 266 MHz w/32MB
            1332 = 366 MHz w/32MB
            1342 = 366 MHz w/64MB
            1352 = 366 MHz w/128MB
            1362 = 366 MHz w/256MB

The MCPN750 transition module designation is TMCPN710. The transition module contains two RJ45 connectors providing access to the asynchronous serial ports permanently configured as EIA DTE, and two HD-26 connectors providing access to two serial ports (COM3 and COM4). For more information refer to the Motorola manual <"TMCPN710 Transition Module Installation and Use">.

The BAT registers are not supported in the current cache management strategy; therefore, they can best be used for non-cacheable, data-only address regions.

Boot ROMS

The MCPN750 boards have two sets of flash EEPROM (FLASH). One set of two AMD Am29F040 FLASH is socketed (sockets XU1 and XU2) and contains Motorola's PPC1-Bug. The other set of E28f800 FLASH is soldered in. The VxWorks boot kernel resides in the soldered FLASH. See Hardware Details: ROM Considerations for information about loading and writing the boot kernel image to the soldered FLASH.

These boards have non-volatile RAM; thus, boot parameters are preserved whenever the system is powered off.

To load VxWorks, and for more information, follow the instructions in the Tornado User's Guide: Getting Started.

Jumpers

The following jumpers are relevant to VxWorks configuration:

MCPN750
Jumper	Function	Description
J7	ROM controller	Install the jumper across pins 2 and 3 to select the socketed FLASH.
		Install the jumper across pins 1 and 2 to select the soldered FLASH
		(factory configuration).

For details of jumper configuration, see the board diagram at the end of this entry and in the hardware manual.

Note that ROM controller jumpers should be set to select socketed FLASH until VxWorks boot code is written to soldered FLASH, after which the jumpers should be restored to the factory configuration of soldered FLASH.

FEATURES

The following subsections list all supported and unsupported features, as well as any feature interaction.

Supported Features

The following features of the MCPN750 are supported:

Feature	Description
Processors	MPC750; 66MHz bus clock
L2 Cache	1MB in-line cache, write-through only.
FLASH	4MB soldered (64-bit wide), 1MB socketed
	(16-bit wide). Soldered used for VxWorks boot image.
DRAM	16, 32, 64, 128MB, two-way interleaved; auto-sized or fixed
NVRAM	8KB (MK48T59/559)
	8KB
Peripherals	Four 16550C asynchronous serial ports COM1, COM2, COM3, and COM4;
	AUI or 10baseT/100baseTX Ethernet interface;
	Primary ATA/EIDE port and Compact Flash;
	USB ports 1 and 2
ISA Interface	full 64KB memory and I/O space
PCI Interface	32-bit address, 32-bit data; complies with PCI Local Bus Specification,
	Revision 2.1
Miscellaneous	RESET switch

Booting the MCPN750

When running with an MCP750 in the same chassis, a reset performed on the MCP750 will automatically reset all MCPN750s in the same chassis. Also, it generally makes no sense to reset (using the reset button) a single MCPN750 in a chassis without resetting the MCP750 as well. The MCP750 PCI autoconfiguration (see below) only enumerates and initializes the PCI bus during MCP750 initialization. Part of this PCI bus initialization involves the MCP750's programming of the MCPN750's Dec2155x downstream BARs. Thus a single MCPN750 which is reset via the reset button press without rebooting the the MCP750 will not be visible to the MCP750 and will be unable to partake in interrupt handshaking or shared memory support. Note that performing a ctrl-x type reboot on the MCPN750 (as opposed to a reset button press) will not destroy the programming in the downstream BAR and the MCPN750 will still be visible to the MCP750 and will be able to partake in interrupt handshaking etc.

PCI Autoconfiguration

The board support package for the MCPN750 handles automatic detection and configuration of compact PCI devices. In particular, it performs the following:

1)

Probes the host PCI bridge for all devices on the host PCI bus (bus zero). Note that among the devices on bus zero might be PCI-PCI bridges. These bridges are probed as well and recursive probing occurs until all devices and bridges are found.

2)

Memory is assigned to each device and sub-bridge found. For devices, each Base Address Register (BAR) is queried. Memory or I/O space (or both) is allocated for each BAR which has been implemented.

3)

Complete initialization of the devices is performed, including cache Line size, command register, latency timer, interrupt line and base address registers (0 through 5). PCI-PCI bridges are initialized with the correct primary bus, secondary bus and subordinate bus designation. In short, the entire bridge/device "tree" rooted at the host pci bridge is completely configured and ready for driver access.

PCI Autoconfiguration Roll Call

A new feature to the PCI autoconfiguration is "roll call". If you expect to find a certain number of specific devices identified by device/vendor ID during PCI autoconfiguration you can enter the information into a roll call list. For example assume that you know that the autoconfiguration process should find 4 different devices with device/vendor ID of 0x00461011 (this would be the Dec2155x device). You want PCI autoconfiguration to "wait" until it finds at least this many but you don't want it to wait more than 20 seconds. If 20 seconds have elapsed and 4 different Dec2155x chips have not appeared in the bus enumeration process, you would like the PCI autoconfiguration process to proceed anyway.

You would construct the "roll call" list in "config.h" as shown below:

#define ROLL_CALL_MAX_DURATION 20

#define PCI_ROLL_CALL_LIST_ENTRIES \ { 4, 0x00461011 },

The parameter ROLL_CALL_MAX_DURATION specifies that no more than 20 seconds should elapse before proceeding on with the autoconfiguration, even though less than 4 Dec2155x devices have been found.

You can see the entry { 4, 0x00461011 } which says that you expect to find at least 4 devices whose device/vendor ID is 0x00461011. Note that "mcpx750.h" contains defines for some device/vendor IDs, such a define could be used here instead of a hard-coded device/vendor ID.

Also note that this list can be extended so more than one device/ vendor ID is identified with possibly a different count.

If the list is empty (except for the termination entry) then there is no roll call waiting performed, regardless of the setting of ROLL_CALL_MAX_DURATION (seconds).

The roll call feature can be useful for devices which are slow to appear on the cPCI bus. For example, MCPN750 CPU boards (which contain the Dec2155x nontransparent PCI bridge) will not be visible to an MCP750 master which is enumerating the bus until the MCPN750 clears the "primary access lock-out" bit in the Dec2155x chip control 0 register. If the MCP750's bus enumeration occurs before the MCPN750 software unlocks the Dec2155x, then the MCP750 will not know the MCPN750 is present and will not configure it. The roll call feature allows for bus enumeration polling until the specified devices actually appear. Note that roll call may not always be required for the example just presented. Some system configurations and timings may work without using the roll call feature.

Dec2155x PCI-to-PCI Non-Transparent Bridge Support

This BSP contains support for the Dec2155x non-transparent PCI-to-PCI bridge. This device provides read/write access to and from the Compact PCI bus (cPCI).

The following support is provided:

Up to 4 user configurable downstream cPCI to local PCI windows.
Up to 2 user configurable upstream local PCI to cPCI windows.
Support for in-bound "doorbell" interrupts.
Support for cPCI backpanel interrupts.
cPCI to local CPU address translation.
Local CPU to cPCI address translation.
Build-time validation of Dec2155x configuration parameters.

Dec2155x Support Limitations

The PReP standard does not support 64-bit PCI addressing. Therefore, this BSP does not provide support for 64-bit addressing through the Dec2155x.

There is a limitation when the cPCI to local PCI or cPCI to local CPU address translation routines are presented with a cPCI address which maps into a downstream window on the local board. The translation will succeed and return an address, but when that address is accessed, the Dec2155x will attempt to access one of its own downstream windows. The transfer will fail because PCI devices cannot access themselves on the cPCI bus. Depending on how error detection is configured, the result will be invalid data or a PCI Master Abort.

Interrupt vectors are provided for the interrupts associated with Dec2155x Hot Swap Power State transitions, Intelligent I/O (I2O), and the Upstream Memory 2 Base Address Register but no other support for these features is provided.

During system startup, the Dec2155x must be configured and unlocked before the host enumerates the cPCI bus. To meet this timing requirement, the Dec2155x is configured by the vxWorks boot ROM image. If changes to the Dec2155x configuration are made, new boot ROMs are required in addition to a new kernel. For proper operation, the Dec2155x configuration in the Boot ROMs must match the configuration used by the kernel.

The Dec2155x places certain limitations on window sizes and translation values. This BSP adheres to those limitations and provides build-time parameter checking to help avoid misconfigurations. Modifications to the default Dec2155x configuration provided in this BSP must be made with care to avoid invalid configurations. Information on the default Dec2155x configuration provided by this BSP is presented in the next section and modification guidelines appear later in this file.

Dec2155x Default Configuration

The default Dec2155x configuration supports a host processor (MCP750) and up to 7 MCPN750s. The following interoperability is supported:

Host access to MCPN750 CSR and the low 4MB of MCPN750 DRAM.
MCPN750 access to the low 4MB of host DRAM.
MCPN750 access to peer MCPN750 CSR and low 4MB of peer MCPN750 DRAM.

.P The BSP provides these features using the following Dec2155x configuration:

Primary CSR and Downstream Memory 0 BAR:
Size:	4MB
Direction:	In-Bound (cPCI to MCPN750)
cPCI Adrs:	Dynamic (assigned by host)
Local PCI Adrs:	PCI_SLV_MEM_BUS (0x80000000 by convention)
Local CPU Adrs:	PCI_SLV_MEM_LOCAL (0x00000000 by convention)
Use:	R/W access to CSR (low 4KB) and MCPN750 DRAM (above 4KB)

Upstream I/O or Memory 0 BAR:
Size:	4MB
Direction:	Out-Bound (MCPN750 to cPCI)
cPCI Adrs:	CPCI_MSTR_MEM_BUS (0x80000000 by convention)
Local PCI Adrs:	Dynamic (assigned by MCPN750)
Local CPU Adrs:	Dynamic (based on local PCI adrs)
Use:	R/W access to host DRAM

Upstream Memory 1 BAR:
Size:	32MB
Direction:	Out-Bound (MCPN750 to cPCI)
cPCI Adrs:	Base cPCI address of the host's dynamic PCI configuration area (0x02000000 for
	the default MCP750 BSP)
Local PCI Adrs:	Dynamic (assigned by MCPN750)
Local CPU Adrs:	Dynamic (based on local PCI adrs)
Use:	R/W access to cPCI devices

The remaining Dec2155x Base Address Registers are not used by the BSP and are available for use by the application.

Dec2155x Address Translation:

Due to the dynamic nature of PCI address allocation, the locations of the upstream Dec2155x windows move as devices are added to the MCPN750 PCI bus. Since these windows map the cPCI space into the local MCPN750 PCI and CPU address spaces, their positions determine where the cPCI resources appear when viewed by the MCPN750 CPU and any MCPN750 resident PCI devices. Likewise, the downstream windows move as cPCI devices are added and removed. The downstream windows are used to map the on-board PCI and DRAM resources into the cPCI address space for access by the host and other cPCI devices.

To assist with address translation, two translation routines are provided by this BSP:

sysLocalToBusAdrs( )	Translates a local CPU address to an equivalent cPCI or local PCI memory or
	I/O address.
sysBusToLocalAdrs( )	Translates a cPCI or local PCI memory or I/O space address to a local CPU
	equivalent address.

.HP 6

NOTE

The translations performed by sysLocalToBusAdrs( ) and sysBusToLocalAdrs( ) are not symmetrical if one of the endpoints is the Compact PCI bus. sysLocalToBusAdrs( ) translates by locating a downstream window which makes the local CPU address visible in the cPCI address space. sysBusToLocalAdrs( ) performs a similar operation by locating an upstream window which makes the cPCI address visible in the local CPU address space. Since the two sets of windows map different areas of the local address space, the translation is not reversible.

Accessing Dec2155x CSR Registers

Due to dynamic PCI address allocation, the PCI address assigned to the Dec2155x CSR area cannot be known until runtime. To determine the assigned address, it is necessary to read the Secondary CSR memory BAR (or the Secondary CSR I/O BAR if I/O space is to be used).

The following code fragment derives the CPU address of the Scratchpad 0 register using its PCI memory space address:

    UINT32 bar;

    /* get the contents of the secondary CSR memory BAR
       (see note below) */

    if (pciConfigInLong (0, DEC2155X_PCI_DEV_NUMBER, 0,
                         DEC2155X_CFG_SEC_CSR_MEM_BAR,
                         &bar) != OK)
        {
        return (ERROR);
        }

    /* calculate the local PCI address of the scratchpad 0
       register */

    bar += DEC2155X_CSR_SCRATCHPAD0;

    /* convert the result to the CPU equivalent address */

    if (sysBusToLocalAdrs (PCI_SPACE_MEM_PRI, (char *)bar,
                         (char **)&bar) != OK)
        {
        return (ERROR);
        }

    return (bar);

.HP 6

NOTE

Using the constant DEC2155X_PCI_DEV_NUMBER ensures that the on-board Dec2155x is read. If a search of the local PCI bus had been performed using the Dec2155x device ID, the returned Bus, Device and Function numbers may have corresponded to a Dec2155x part found on an installed PMC card.

.P Once the local CPU address is known, the cPCI address can be derived by adding the following code fragment before returning the result:

    if (sysLocalToBusAdrs (PCI_BACKPANEL_MEMORY_SPACE,
                           (char *)bar,
                           (char **)&bar) != OK)
        return (ERROR);
    else
        return (bar); \ce

Internal Dec2155x Interrupt Sources

At start-up, all Dec2155x interrupt sources are masked and cleared. Before unmasking an interrupt, an application ISR service routine must be attached to the appropriate Dec2155x interrupt vector using intConnect( ). Multiple ISR service routines can be connected to each vector if required by the application. Once the handler is attached, the interrupt can be enabled and disabled by calling sysDec2155xIntEnable( ) or sysDec2155xIntDisable( ) as required. Interrupt vector definitions for the Dec2155x internal interrupt sources are defined in mcpx750.h.

Unique interrupt vectors are provided for each of the 16 bits in the Dec2155x Secondary IRQ register. Bit 0 (LSB) corresponds to DEC2155X_DOORBELL0_INT_VEC with the remaining bits mapped in sequence. These doorbell interrupts can be used for host-to-MCPN750 or MCPN750-to-MCPN750 event notification. The Dec2155x interrupt handler clears these interrupts which simplifies the application ISR.

Individual interrupt vectors are also provided for Dec2155x Hot Swap Power State and I2O in-bound list events. The Dec2155x interrupt handler also clears these interrupts.

The 64 Upstream Memory 2 BAR Page Crossing interrupts are all presented on a single interrupt vector and the application ISR is responsible for clearing the bits serviced. Calls to sysDec2155xIntEnable( ) and sysDec2155xIntDisable( ) enable or disable all 64 interrupts.

The Dec2155x interrupt handler provides a default service routine for all unclaimed interrupt vectors, including the Upstream Memory 2 BAR Page Crossing interrupt. The default routine reports the event and clears the interrupt source.

Compact PCI Backpanel Interrupts

The Dec2155x can generate cPCI backpanel interrupts using any of the bits in the Primary IRQ register if they have been un-masked by the host. The following code fragment generates a compact PCI backpanel interrupt by setting bit 15 (MSB) of the Primary IRQ register:

    if (sysBusIntGen (DEC2155X_DOORBELL15_INT_LVL,
                      DEC2155X_DOORBELL15_INT_VEC) != OK)
        return (ERROR);

Note that the cPCI bus does not provide an interrupt vector to the host. The vector number passed to sysBusIntGen( ) simply identifies which bit in the register to set. It is the host's responsibility to locate the interrupt source and clear the interrupt.

In-bound cPCI backpanel interrupts are routed directed to the MCPN750 Raven MPIC and can be enabled, disabled and handled by calling sysIntEnable( ), sysIntDisable( ) and intConnect( ) with the MPIC vector number of the desired backpanel interrupt line. By default, cPCI backpanel interrupts are disabled for the MCPN750 in config.h. It is recommended that these interrupts be left disabled to prevent interaction problems with the MCP750 and cPCI system operation.

.HP 6

NOTE

Great care must be exercised when cPCI backpanel interrupts are being generated and received simultaneously. If the packpanel interrupt line driven by the MCPN750 is also enabled for receiving interrupts, the MCPN750 will be interrupted by its own backpanel interrupt. This scenario causes complications because the backpanel interrupts are configured as level sensitive and difficulties are encountered in determining the party responsible for clearing the interrupt source. In general, backpanel interrupt generation is useful for signaling an event to the host, but in-bound packpanel interrupts have limited usefulness.

Altering the Default Dec2155x Configuration:

Altering the Dec2155x configuration requires the careful consideration of several items:

Dec2155x window sizes and alignment.
Dec2155x translation values.
The size and alignment of the host's dynamic PCI configuration area.
The size and alignment of the MCPN750's dynamic PCI configuration area.

.P The Dec2155x window parameters are controlled by #defines in config.h. There are three defines associated with each window:

..._SIZE	determines the size of the window in bytes and must be an
	integral power of two. The minimum size for a PCI I/O
	space window is 64 bytes. The minimum size for a PCI
	memory space window is 4KB. To disable a window, set the
	size to 0. Note that the Dec2155x will not allow the
	Primary CSR and Downstream Memory 0 BAR to 0 to be
	disabled. If the size of this window is set to zero, the
	Dec2155x will default to a 4KB window.
NOTE:	If a window value is not a power of 2, or is below the minimum size, sysLib.c
	will not compile.

..._TYPE	determines the type of the window and any placement
	restrictions. For proper operation, the window must be
	configured for placement anywhere in the 32-bit PCI
	address space.

..._TRANS	determines the base address of the window on the target
	PCI bus. It is important to remember that this is a local
	PCI address (downstream window) or a cPCI address
	(upstream window). The translation value chosen must be
	an even multiple if the window size.
NOTE:	If the translation value is not a multiple of the window
	size, sysLib.c will not build.

The default window sizes can be reduced without altering the sizes of the dynamic PCI configuration area. However, if the required values are significantly reduced from the default values, reducing the size of the dynamic PCI configuration area reduces the size of the MMU page tables at the ratio of 128:1 (a 128KB reduction saves 1KB of MMU table space).

The size of the PCI memory space used for dynamic PCI configuration is controlled by PCI_MSTR_MEMIO_LOCAL in config.h and the area's base address is controlled by PCI_MSTR_MEMIO_BUS in mcpx750.h. By default, the companion MCP750 BSP allocates a 32MB area aligned to a 32MB boundary for dynamic PCI configuration. To access peer MCPN750 DRAM areas, an upstream window must be opened which matches the size of the host's dynamic PCI configuration area. For translation to work correctly, the host's dynamic PCI configuration area must be aligned to a multiple of the area's size and the corresponding Dec2155x upstream translation register must contain the area's base cPCI address (not CPU address). Since this BSP supports peer-to-peer access between MCPN750 DRAM areas, the default dynamic PCI configuration area for the MCPN750 is 64MB aligned to a 32MB boundary which satisfies these requirements.

In addition to the peer access window, sufficient space must also be available for mapping the host DRAM upstream window and any space required by MCPN750-resident PCI devices. A margin must also be allowed for areas that are unusable due to window alignment requirements.

If the application does not require peer-to-peer MCPN750 DRAM access, the large 32MB window used to contain the host's dynamic PCI configuration area can be eliminated with a corresponding decrease in the required MCPN750 dynamic PCI configuration area. If peer-to-peer doorbell interrupts are still required, the doorbell interrupt registers of peer MCPN750s may be accessed through an I/O window which has much smaller CPU address space requirements. This would require re-configuring the default BSP to access host DRAM through Upstream Memory 1 BAR and using the Upstream I/O or Memory 0 BAR to access the peer MCPN750 doorbell interrupt registers.

Shared Memory Support

The MPCN750 supports shared memory backplane communication with the MCP750 or CPV5000 as the Compact PCI host node. The Wind River documentation provides a great deal of information regarding shared memory concepts. The section below provides tutorial style information regarding the setup of a shared memory system involving the MCPN750 and either a MCP750 or a CPV5000.

Setting up a working shared memory system involves proper setting of certain "config.h" parameters and proper setting of boot parameters via the "c" command from the boot prompt. There are three components involved in shared memory communication which must be configured properly to create a working system:

Anchor:

This is an area of memory which must be accessible to all nodes participating in shared memory backplane communication. The anchor points to the actual shared memory buffer pool which must be located in the same memory space as the anchor itself. The associated "config.h" parameter is SM_ANCHOR_ADRS. In certain configurations, nonzero nodes will "poll" for the location of the anchor. "config.h" defines which comes into play for polling are SM_OFF_BOARD and SYS_SM_SYSTEM_MEM_POLL.

Master node:

This node is always designated as node zero. It is the node which sets up the anchor and shared memory pool. Once the anchor and shared memory pool is set up, the master node acts as a peer with the other nodes. The node number (0 in this case) is one of the boot parameters which can be set up with the "c" command from the bootline prompt.

Sequential addressing:

This is is governed by a "config.h" parameter, INCLUDE_SM_SEQ_ADDR and is used when sequential IP addresses are assigned to the participating nodes. Node zero is assigned the lowest IP address, followed by nodes 1, 2 etc. which are assigned the subsequent and sequential IP addresses. The advantage of sequential addressing is that fewer boot parameters must be specified to configure the system.

The following restrictions apply to shared memory configurations.

1)

Node zero must not boot over the shared memory interface. Only nonzero nodes are allowed to boot over the shared memory "sm" interface.

2)

The location of the anchor must be statically determinable by the master node (node 0). That is, the location of the anchor must either be a build-time static parameter or it must be able to be communicated to the master node via the "sm=xxxxxxxx" boot configuration parameter. The nonzero nodes need not know the location of the anchor at build or boot time but can be configured to poll for the anchor dynamically.

Note: Another piece of shared memory terminology is "host node". The "host node" is the node which configures the compact PCI bus during startup initialization. In a system consisting of an MCP750 and one or more MCPN750s, the "host node" is the MCP750. Don't confuse "host node" with "master node". "Master node" is simply a synonym for "node 0". The "host node" may or may not be the "master node". Note also that the "host node" need not necessarily be a VxWorks node.

Below are the crucial "config.h" parameters involved in shared memory:

CPCI_MSTR_MEM_BUS (address):

The parameter is used to identify the address where the system DRAM will be configured at. This is dependent on the host board used and is defined in "config.h". The explaination says to set the value to 0x80000000 for a MCP750 host (default) or 0x00000000 for a CPV5000 host.

SM_OFF_BOARD (TRUE or FALSE):

The parameter has a configurable value of either TRUE or FALSE and directly determines the value of SM_ANCHOR_ADRS (the anchor address).

If SM_OFF_BOARD is defined as FALSE, then the anchor is on-board and SM_ANCHOR_ADRS is defined to be LOCAL_MEM_LOCAL_ADRS + SM_ANCHOR_OFFSET. LOCAL_MEM_LOCAL_ADRS is defined as 0x0 in "config.h" and SM_ANCHOR_OFFSET is defined as 0x4100 in "config.h" to work with an MCP750. SM_ANCHOR_OFFSET needs to be changed to 0x1100 in "config.h" to work with a CPV5000.

If defined as TRUE, then SM_ANCHOR_ADRS is defined as a function call: sysSmAnchorAdrs( ) (defined in "sysLib.c"). This function will dynamically poll, at system startup, various locations (explained below) for the exact location of the shared memory anchor.

Note that if "sm=xxxxxxxx" is used as a boot parameter, then SM_OFF_BOARD has no effect. The value of "xxxxxxxx" will be used as the anchor location regardless of the setting of SM_OFF_BOARD. If simply "sm" is used as a boot parameter, then SM_OFF_BOARD is queried at initialization time to determine if polling is required or not.

SYS_SM_SYSTEM_MEM_POLL (#define or #undef):

This define only has an effect if anchor polling is called for (because SM_OFF_BOARD is defined as TRUE and "sm" is used with no "=xxxxxxxx"). In this case, simply defining SYS_SM_SYSTEM_MEM_POLL will cause the node to poll for the anchor at compact PCI bus address CPCI_MSTR_MEM_BUS + SM_ANCHOR_OFFSET (0x80004100). "System memory" (which is the host node's DRAM) will be included as one of the locations where the anchor might reside. Note that other locations my be polled as well (explained later).

Not defining SYS_SM_SYSTEM_MEM_POLL will prevent the polling of system memory for the anchor.

SYS_SM_ANCHOR_POLL_LIST (#define or #undef):

This define has an effect only if polling is called for (see SM_OFF_BOARD explained above). When defined, SYS_SM_ANCHOR_POLL_LIST allows a list of devices, identified by device/vendor ID and subsystem ID/subsystem vendor ID to be specified as candidates for the anchor location. Devices which appear directly on the compact PCI bus are found and if they appear on the list defined by SYS_SM_ANCHOR_POLL_LIST, they are checked to see if they house the shared memory anchor. The memory defined by the first memory BAR is queried at offset SM_ANCHOR_OFFSET (0x4100 by default, defined in "config.h"). If SYS_SM_ANCHOR_POLL_LIST is not defined, ALL devices on the compact PCI bus will be considered candidates for the anchor location and will be polled. If SYS_SM_ANCHOR_POLL_LIST defined but empty, NO devices on the compact PCI bus will be considered candidates for the anchor location. In that case, the only location polled would be system memory if SYS_SM_SYSTEM_MEM_POLL (see above) was defined.

INCLUDE_SM_SEQ_ADDR (#define or #undef)

If "undef'ed", sequential addressing is disabled. This symbol is defined by default.

Consider a system consisting of an MCP750 (host node) and two MCPN750s. The following six configurations are the only ones possible:

	Master node on...	Anchor on...	Sequential Addressing?
1.	MCP750	MCP750	NO
2.	MCP750	MCP750	YES
3.	MCPN750	MCP750	NO
4.	MCPN750	MCP750	YES
5.	MCPN750	MCPN750	NO
6.	MCPN750	MCPN750	YES

NOTE

Master node on MCPN750 and Anchor on CPV5000 is not supported.

Below is a description of how each of the above systems would be configured. Crucial "config.h" and boot parameter settings for an example system are given. In each example, SYS_SM_ANCHOR_POLL_LIST was defined to contain information identifying the Dec2155x bridge chip (present on the MCPN750). See "config.h" for the example of how this was done.

1)

MCP750 master, MCP750 anchor, no sequential addressing:

   MCP750:

        #define SM_OFF_BOARD FALSE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        #undef  INCLUDE_SM_SEQ_ADDR

        boot device          : dc
        host name            : sunray
        processor number     : 0
        inet on ethernet (e) : 124.170.16.112
        inet on backplane (b): 124.200.200.1:ffffff00
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.170.16.233
        target name (tn)     : gamma

   MCPN750-1:

        #define SM_OFF_BOARD TRUE
        #define SYS_SM_SYSTEM_MEM_POLL
        #undef  INCLUDE_SM_SEQ_ADDR

        boot device          : sm
        host name            : sunray
        processor number     : 1
        inet on ethernet (e) : 124.170.16.109
        inet on backplane (b): 124.200.200.2
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.200.200.1
        target name (tn)     : alpha

   MCPN750-2:

        (same "config.h" setup as MCPN750-1 above)

        boot device          : sm
        host name            : sunray
        processor number     : 2
        inet on ethernet (e) : 124.170.16.110
        inet on backplane (b): 124.200.200.3
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.200.200.1
        target name (tn)     : beta

2)

MCP750 master, MCP750 anchor, sequential addressing:

   MCP750:

        #define SM_OFF_BOARD FALSE
        #define SYS_CPCI_BUS_NUMBER    1
        #undef SYS_SM_SYSTEM_MEM_POLL
        /* #undef INCLUDE_SM_SEQ_ADDR */

        boot device          : dc
        host name            : sunray
        processor number     : 0
        inet on ethernet (e) : 124.170.16.112:ffffff00
        inet on backplane (b): 124.200.200.1:ffffff00
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.170.16.233
        target name (tn)     : gamma


   MCPN750-1:

        #define SM_OFF_BOARD TRUE
        #define SYS_CPCI_BUS_NUMBER    1
        #define SYS_SM_SYSTEM_MEM_POLL
        /* #undef INCLUDE_SM_SEQ_ADDR */

        boot device          : sm
        host name            : sunray
        processor number     : 1
        inet on ethernet (e) :
        inet on backplane (b):
        host inet (h)        : 124.170.16.143
        gateway inet (g)     :
        target name (tn)     : alpha


   MCPN750-2:

        (same "config.h" setup as MCPN750-1 above)

        boot device          : sm
        host name            : sunray
        processor number     : 2
        inet on ethernet (e) :
        inet on backplane (b):
        host inet (h)        : 124.170.16.143
        gateway inet (g)     :
        target name (tn)     : beta

3)

MCPN750 master, MCP750 anchor, no sequential addressing:

   MCP750:

        #define SM_OFF_BOARD FALSE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        #undef  INCLUDE_SM_SEQ_ADDR

        boot device          : sm
        host name            : sunray
        processor number     : 1
        inet on ethernet (e) : 124.170.16.112
        inet on backplane (b): 124.200.200.1
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.200.200.2
        target name (tn)     : gamma

   MCPN750-1:

        #define SM_OFF_BOARD TRUE
        #define SYS_SM_SYSTEM_MEM_POLL
        #undef  INCLUDE_SM_SEQ_ADDR

        boot device          : dc
        processor number     : 0
        host name            : sunray
        inet on ethernet (e) : 124.170.16.109
        inet on backplane (b): 124.200.200.2:ffffff00
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.170.16.233
        target name (tn)     : alpha

   MCPN750-2:

        #define SM_OFF_BOARD TRUE
        #define SYS_SM_SYSTEM_MEM_POLL
        #undef  INCLUDE_SM_SEQ_ADDR

        boot device          : sm
        processor number     : 2
        host name            : sunray
        inet on ethernet (e) : 124.170.16.110
        inet on backplane (b): 124.200.200.3
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.200.200.2
        target name (tn)     : beta

4)

MCPN750 master, MCP750 anchor, sequential addressing:

   MCP750:

        #define SM_OFF_BOARD FALSE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        /* #undef  INCLUDE_SM_SEQ_ADDR */

        boot device          : sm
        processor number     : 1
        host name            : sunray
        inet on ethernet (e) :
        inet on backplane (b):
        host inet (h)        : 124.170.16.143
        gateway inet (g)     :
        target name (tn)     : gamma


   MCPN750-1:

        #define SM_OFF_BOARD TRUE
        #define SYS_CPCI_BUS_NUMBER    1
        #define SYS_SM_SYSTEM_MEM_POLL
        /* #undef  INCLUDE_SM_SEQ_ADDR */

        boot device          : dc
        processor number     : 0
        host name            : sunray
        inet on ethernet (e) : 124.170.16.109:ffffff00
        inet on backplane (b): 124.200.200.1:ffffff00
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.170.16.233
        target name (tn)     : alpha

   MCPN750-2:

        #define SM_OFF_BOARD TRUE
        #define SYS_CPCI_BUS_NUMBER    1
        #define SYS_SM_SYSTEM_MEM_POLL
        /* #undef  INCLUDE_SM_SEQ_ADDR */

        boot device          : sm
        processor number     : 2
        host name            : sunray
        inet on ethernet (e) :
        inet on backplane (b):
        host inet (h)        : 124.170.16.143
        gateway inet (g)     :
        target name (tn)     : beta

5)

MCPN750 master, MCPN750 anchor, no sequential addressing:

   MCP750:

        #define SM_OFF_BOARD TRUE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        #undef  INCLUDE_SM_SEQ_ADDR

        boot device          : sm
        processor number     : 1
        host name            : sunray
        inet on ethernet (e) : 124.170.16.112
        inet on backplane (b): 124.200.200.1
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.200.200.2
        user (u)             : ball
        ftp password (pw) (blank = use rsh):
        flags (f)            : 0x0
        target name (tn)     : gamma


   MCPN750-1:

        #define SM_OFF_BOARD FALSE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        #undef  INCLUDE_SM_SEQ_ADDR

        boot device          : dc
        processor number     : 0
        host name            : sunray
        inet on ethernet (e) : 124.170.16.109
        inet on backplane (b): 124.200.200.2:ffffff00
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.170.16.233
        target name (tn)     : alpha

   MCPN750-2:

        #define SM_OFF_BOARD TRUE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        #undef  INCLUDE_SM_SEQ_ADDR

        boot device          : sm
        processor number     : 2
        host name            : sunray
        inet on ethernet (e) : 124.170.16.110
        inet on backplane (b): 124.200.200.3
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.200.200.2
        target name (tn)     : beta

6)

MCPN750 master, MCPN750 anchor, sequential addressing:

   MCP750:

        #define SM_OFF_BOARD TRUE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        /* #undef  INCLUDE_SM_SEQ_ADDR */

        boot device          : sm
        processor number     : 1
        host name            : sunray
        inet on ethernet (e) :
        inet on backplane (b):
        host inet (h)        : 124.170.16.143
        gateway inet (g)     :
        target name (tn)     : gamma

   MCPN750-1:

        #define SM_OFF_BOARD FALSE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        /* #undef  INCLUDE_SM_SEQ_ADDR */

        boot device          : dc
        processor number     : 0
        host name            : sunray
        inet on ethernet (e) : 124.170.16.109:ffffff00
        inet on backplane (b): 124.200.200.1:ffffff00
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.170.16.233
        target name (tn)     : alpha

   MCPN750-2:

        #define SM_OFF_BOARD TRUE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        /* #undef  INCLUDE_SM_SEQ_ADDR */

        boot device          : sm
        processor number     : 2
        host name            : sunray
        inet on ethernet (e) :
        inet on backplane (b):
        host inet (h)        : 124.170.16.143
        gateway inet (g)     :
        flags (f)            : 0x0
        target name (tn)     : beta

Unsupported Features

The following board features are not supported:

Feature	Description
RTC	MK48T59/559; only NVRAM portion is used
Peripherals	SROM (I2C interface).
ISA Interface	ISA RTC.
PCI Interface	64-bit data; Prefetchable memory is not distinguished from nonprefetchable.
Compact PCI	Compact PCI device autoconfiguration and compact PCI bus interrupt handling.
Hot Swap	No software support for hot swap.
Registers	No support for Board Status and Board Last Reset registers.
Timers	Watchdog timers.

Feature Interactions

MPIC Spurious Interrupts

A race condition can exist between PCI write posting and interrupt processing which can cause an MPIC spurious interrupt. The problem occurs when a device's interrupt service routine writes to clear the interrupt source and then returns to the interrupted code. When the PCI bus is very busy, the write takes a while to get onto the bus and reach the interrupting device. During this time, the device's interrupt will remain asserted. If the PowerPC reenables external interrupts before the PCI write has reached the interrupting device, the processor will see the interrupt still asserted and re-enter the MPIC interrupt routines.

When the MPIC handler reads the vector, the MPIC reports a spurious interrupt because the PCI write has generally completed by then and the device's interrupt has now been cleared.

Spurious Interrupt Workaround

Modify the driver to perform a read from the PCI device (after writing to the device to clear the interrupt) to ensure that the write has fully propagated. sysPciOutWordConfirm( ) will do this automatically. Note that sysPciOutWordConfirm( ) reads from the address written which may cause an undesirable side-effect depending on the design of the hardware. If it does, just add a read from any safe location on the device. The primary goal is force the write out of the posting queues before proceeding.

HARDWARE DETAILS

This section details device drivers and board hardware elements.

Devices

The device drivers and libraries included with this BSP:

i8250Sio:	Intel 8250 UART driver (serial ports 1 and 2).
ppcDecTimer:	PowerPC decrementer timer driver (system clock).
ravenAuxClk:	Motorola Raven timer driver for auxiliary clock.
ravenMpic:	Motorola Raven MPIC interrupt controller driver.
ravenPci:	Motorola Raven PCI bus bridge chip driver.
pciAutoConfigLib:	PCI autoconfiguration library.
pciConfigLib:	PCI configuration library.
pciConfigShow:	Show routines of PCI bus library.
dec21x40End:	10baseT/100baseTX DEC 21x4x Ethernet driver.
byteNvRam:	byte-oriented generic non-volatile RAM driver.
ns8730xSuperIo:	National Semiconductor 8730x Super IO driver.
ataDrv:	ATA/IDE (LOCAL and PCMCIA) disk device driver.
isaDma:	DMA controller device (I8237) utilities/support driver.
fdcDrv:	driver for PS2 floppy device controller(FDC)
dec2155xCpci.c:	DEC 2155x Non-Transparent PCI-to-PCI Bridge support.
vpd:	Vital Product Data Support.
hawkI2c:	Falcon/Hawk I2C support.

Memory Maps

On-board RAM for these boards always appears at address 0x0 locally.

Dynamic memory sizing is supported. By default, LOCAL_MEM_AUTOSIZE is defined so memory is auto-sized at hardware initialization time. If auto-sizing is not selected, LOCAL_MEM_SIZE must be set to the actual size of DRAM memory available on the board to ensure all memory is available. The default fixed RAM size is set to 16MB (see LOCAL_MEM_SIZE in config.h).

Interrupts

The system interrupt vector table has 256 entries. Vectors for the various devices on the buses are assigned hierarchically as follows:

Vector#	Assigned to
00 - 0f	ISA IRQ numbers 0 - 15
10 - 1f	All MPIC interrupts
20 - 23	Raven timers
24 - 27	Raven interprocessor dispatch
28	Raven detected internal errors
29 - 5f	[User defined]
60 - 72	Dec2155x interrupts
73 - ff	[User defined]

The specific ISA vector number assignments are:

Vector#	Assigned to
02	[Cascade interrupt from PIC2]
03	COM2 and COM4
04	COM1 and COM3

Vector numbers not in the table are not used by this BSP.

The standard ISA Intel 8259 Programmable Interrupt Controllers (PICs) assert their interrupts through the Raven MPIC as an external interrupt. The external interrupt vector numbers (MPIC vectors) are:

Vector#	Assigned to
10	PBC (8259)
11	Falcon-ECC error
12	PCI Ethernet
13	Watchdog Timer Level 1
14	Dec2155x
15	CompactPCI Bus1 INTA#
16	CompactPCI Bus1 INTB#
17	CompactPCI Bus1 INTC#
18	CompactPCI Bus1 INTD#
19	PMC1 INTA#/PMC2 INTB#
1a	PMC1 INTB#/PMC2 INTC#
1b	PMC1 INTC#/PMC2 INTD#
1c	PMC1 INTD#/PMC2 INTA#

Vector numbers not in the table are not used by this BSP.

The Raven Multi-Processor Interrupt Controller (MPIC) sets system interrupt priorities and serves as controller of all external interrupts. Each of its 16 interrupt control registers, designated IRQ0 through IRQ15, can be programmed with a relative priority from 15, the highest, to 0, the lowest. A priority of zero effectively disables the interrupt. All but one of the 16 control registers has been hardwired to a particular interrupt source. The IRQ number and priority assignments are as follows:

Raven MPIC IRQ	Priority	IRQ Source
IRQ0	8	PBC (8259)
IRQ1	0	Falcon ECC Error
IRQ2	14	Ethernet
IRQ3	0	Watchdog Timer Level 1
IRQ4	10	Dec2155x
IRQ5	0	CompactPCI Bus 1 INTA#
IRQ6	0	CompactPCI Bus 1 INTB#
IRQ7	0	CompactPCI Bus 1 INTC#
IRQ8	0	CompactPCI Bus 1 INTD#
IRQ9	3	PMC1 INTA#/PMC2 INTB#
IRQ10	3	PMC1 INTB#/PMC2 INTC#
IRQ11	3	PMC1 INTC#/PMC2 INTD#
IRQ12	3	PMC1 INTD#/PMC2 INTA#

For further details, refer to the appropriate board's reference guide.

There are only four PCI bus interrupts: A, B, C, and D. They are shared among all PCI bus devices and do not have levels. PCI bus interrupts are wired directly to the MPIC and, therefore, have preassigned system vector numbers and interrupt levels. The MCPN750 default configuration disables these interrupt sources at the MPIC by programming the MPIC relative priority as zero for these interrupt sources (see "config.h"). In normal situations, the board plugged into the "CPU" or "system" slot (a board such as the MCP750) will field these interrupts. Enabling these interrupts sources on the MCPN750 is not recommended (see earlier section titled "Compact PCI Backpanel Interrupts"). Nevertheless, if it is desired to enable these interrupts for the MCPN750, "config.h" must be modified to program the interrupt level for these sources with a value between 1 and 15. The user then enables one or more PCI interrupts and connects vectored ISRs to the system by following these steps:

1)

Identify the PCI interrupt letter(s) as required by the application. Based on this, identify the associated system interrupt vector from the following chart taken from the external (MPIC) interrupt table:

Vector#	Assigned to
19	PMC1 INTA#/PMC2 INTB#
1a	PMC1 INTB#/PMC2 INTC#
1b	PMC1 INTC#/PMC2 INTD#
1c	PMC1 INTD#/PMC2 INTA#

For example, PMC slot 2, INTC# corresponds to vector #1a. The interrupt level (used in the call to intEnable( )) is numerically equal to the interrupt vector number.

2)

In the application code, perform intConnect( ) for each vector and its associated ISR.

3)

Perform IntEnable( ) for each identified system interrupt level.

4)

When the application has finished, perform IntDisable( ) for each identified level.

Serial Configuration

The MCPN750 has four serial ports. All are ISA bus devices (16550C compatible). The console port is labelled COM1. The other ports are COM2, COM3, and COM4.

By default, all serial ports are configured as asynchronous, 9600 baud, with 1 start bit, 8 data bits, 1 stop bit, no parity, and no hardware handshake. Hardware handshake using RTS/CTS is a supported option on all ports.

The TMCPN710 transition module has two RJ-45 connectors for COM1 and COM2; these are permanently configured as DTE. COM3 and COM4 are routed to on-board headers J11 and J14. For details, consult TMCPN710 Transition Module Installation and Use.

Network Configuration

All boards have one Ethernet port which is 10baseT and 100baseTX compatible.

The MCPN750 uses an RJ45 (twisted pair) jack and can be used with either 10baseT or 100baseTX. The Ethernet driver automatically senses and configures the port as 10baseT or 100baseTX. The Ethernet driver is compatible with DEC21040, DEC21140, and DEC21143 devices.

The Media Access Control (Ethernet) address for each port is obtained from a serial ROM contained in the DEC21140 chip. If the address is not found in serial ROM, the driver attempts to read it from NVRAM at offset 0x202c.

Compact Flash Configuration

Compact Flash is supported on the MCPN750 as IDE controller 0, device 0 & 1. To configure the compact flash, perform the following:

1)

In config.h, replace "#undef INCLUDE_ATA" with "#define INCLUDE_ATA".

2)

Set the definitions of ATA_DEV0_STATE and ATA_DEV1_STATE to DEV_PRESENT or DEV_NOT_PRESENT as required.

3)

Rebuild the kernel. After booting, the compact flash device can be configured with the following command:

        usrAtaConfig(0,0,"/ata0") /* Dev 0 */
        usrAtaConfig(0,1,"/ata1") /* Dev 1 */

Universal Serial Bus Configuration

Two USB ports are supported on the MCPN750. They are located on the optional TMCPN710 transition module as J10 and J12. The USB controller is inside the PCI Peripheral Bus Controller (PBC) on the MCPN750 and is HCI v1.1 compatible.

The USB Developer Kit for Tornado is available as an optional product. It includes a USB stack for VxWorks, as well as drivers for various types of USB peripherals. Detailed information can be obtained from the USB Developer Kit documentation.

To enable PCI auto configuration of the USB device, the file sysBusPci.c needs to be modified. In sysPciAutoConfigInclude( ), the case PCI_ID_USB in switch(devVend) should be changed to return OK instead of ERROR. After this change, rebuild and flash a new bootrom by following the instructions in the "ROM Considerations" section. After verifying the new bootrom is functioning properly, proceed to the USB Developer Kit documentation.

Processor Data Bus Parity Configuration

Processor data bus parity checking is supported on the MCPN750 and is enabled by default. .HP 6

NOTE

Do not read the CPU Control Register ($FEF88300) while processor data parity checking is enabled. Reading this register with processor data parity checking enabled may result in a parity error. .P To disable processor data bus parity checking, perform the following:

1)

In config.h, replace "#define INCLUDE_DPE" with "#undef INCLUDE_DPE".

2)

Rebuild the kernel.

Vital Product Data

Support is available for retrieving and displaying Vital Product Data (VPD) from serial EEPROM devices located on the processor board and transition module (if installed.) This data is presented for informational purposes only.

Two VPD Show routines are available as part of this BSP. To access them, perform the following:

1)

In config.h, add "#define INCLUDE_SHOW_ROUTINES".

2)

Rebuild the kernel.

3)

Reboot the system.

4)

At the command line, type "vpdBrdShow" or "vpdTmShow" to display the processor board or transition module VPD information.

.HP 6

NOTE

Reading the serial EEPROMs is performed at system boot time and increases system boot time by 500-600 mSecs. .P If VPD information is not required, it can be eliminated by making the following changes:

1)

In config.h: Change #define INCLUDE_VPD to #undef INCLUDE_VPD.

2)

Rebuild the kernel.

Boot Devices

The supported boot device is:

    dc - Ethernet (10baseT or 100baseTX or AUI)

Motorola's PPC1-Bug can be used to download and run VxWorks. Consult the user's manuals for details.

Flashing the Boot ROM Using Motorola PPC1-Bug: 1

At the PPC1-Bug prompt, set up the network transfer from a TFTP host using niot. Important: You must have a TFTP server running on your host's subnet for the niop command to succeed. Using niot, the Client IP Address, Server IP Address, and Gateway IP Address must be set up for the user's specific environment:

   PPC1-Bug>niot
   Controller LUN =00?
   Device LUN     =00?
   Node Control Memory Address =00FA0000?
   Client IP Address      =123.123.10.100? 123.321.12.123
   Server IP Address      =123.123.18.105? 123.321.21.100
   Subnet IP Address Mask =255.255.255.0?
   Broadcast IP Address   =255.255.255.255?
   Gateway IP Address     =123.123.10.254? 123.321.12.254
   Boot File Name ("NULL" for None)     =? .

   Update Non-Volatile RAM (Y/N)? y
   PPC1-Bug>

The file is transferred from the TFTP host to the target board using the niop command. The file name must be set to the location of the binary file on the TFTP host. The binary file must be stored in the directory identified for TFTP accesses, but the file name is a relative path and does not include the /tftpboot directory name:

   PPC1-Bug>niop
   Controller LUN =00?
   Device LUN     =00?
   Get/Put        =G?
   File Name      =? bootrom.bin
   Memory Address =00004000?
   Length         =00000000?
   Byte Offset    =00000000?

   PPC1-Bug>

After the file is loaded onto the target, the pflash command is used to put it into soldered FLASH parts.

   PPC1-Bug>pflash 4000:FFF00 ff000100

When the command is finished, power down the board and switch the ROM jumper to select soldered FLASH. Then power the board back up.

SPECIAL CONSIDERATIONS

This section describes miscellaneous information concerning this BSP and its use.

Delivered Objects

The delivered objects are: bootrom, bootrom.hex, vxWorks, vxWorks.sym, and vxWorks.st.

Make Targets

The make targets are listed as the names of object-format files. Append .hex to each to derive a hex-format file name.

bootrom

bootrom_uncmp

bootrom_res_high

vxWorks (with vxWorks.sym)

vxWorks.st

vxWorks_rom

vxWorks.st_rom

vxWorks.res_rom_res_low (builds but does not execute)

vxWorks.res_rom_nosym_res_low (builds but does not execute)

Note, "bootrom_res", "vxWorks.res_rom", and "vxWorks.res_rom_nosym" are also make targets but are not part of the PowerPC supported set. These particular targets will not build in the PowerPC environment.

Special Routines

For these boards, the value of the CPU clock speed is read from the CPU configuration register using the macro MEMORY_BUS_SPEED which is defined in mcpx750.h. For example:

   clkFreqMhz = MEMORY_BUS_SPEED;

Known Problems

Spurious transactions on ISA devices

It has been discovered that the VIA PCI-to-ISA bridge device has a subtractive decoder which cannot be disabled. Therefore, when a PCI access is performed to a non-existent PCI I/O or Memory address on the local PCI bus, the VIA PCI-to-ISA bridge will respond and forward the transaction onto the ISA bus using the lower 24 bits of the PCI address as the ISA address. The operation can result in spurious transactions if the resulting ISA address maps to a valid ISA device. If the ISA device does not exist, the PCI-to-ISA bridge returns 0xffffffff if the transaction is a read and discards the data on a write. This behavior prevents the generation of the Master Abort used to detect a faulty local PCI access and essentially nullifies the results of a probe directed at a local PCI I/O or Memory address. If the PCI transaction is claimed by the Dec2155x and forwarded to the cPCI bus, the PCI-to-ISA subtractive decoder does not respond and the Dec2155x will provide the proper response (Target Abort) when an invalid cPCI I/O or Memory address is presented. In this case, the results of the probe are valid. The probe result is also valid if the access references an address that produces an MMU fault regardless of the target address space (local or cPCI I/O or Memory or local DRAM).

Device dc fail to start

Some earlier verions of the MCPN750 boards were shipped with an incorrectly programmed dec21143 SROM. As a result, booting with the END driver will fail with the message "Failed to start device dc." The SROM was mis-programmed with an extra byte inserted at offset 0x20 with a value of 0x03. The rest of the SROM data was shifted down. A mis-programmed SROM appears as follows:

PPC1-Bug>srom
...
$1E (&030) 0008?
$20 (&032) 0301? <---- 0x03 in the upper halfword is the extra byte
$22 (&034) 9303?
...

The following instructions capture how to use PPC1-Bug to remove the extra byte from the SROM. WARNING: Special care must be taken in the following steps, or further corruption of the SROM may result:

PPC1-Bug>srom

Device Address =$00007000 (N/Y)? y
Reading SROM into Local Buffer.....
$00 (&000) 5710?
$02 (&002) 5634?
$04 (&004) 0000?
$06 (&006) 0000?
$08 (&008) 0000?
$0A (&010) 0000?
$0C (&012) 0000?
$0E (&014) 0000?
$10 (&016) 1300?
$12 (&018) 0301?
$14 (&020) 0800?
$16 (&022) 3E28?
$18 (&024) 3DBF?
$1A (&026) 0E1E?
$1C (&028) 0000?
$1E (&030) 0008?
$20 (&032) 0301? 0193
$22 (&034) 9303? 0308
$24 (&036) 0800? 0003
$26 (&038) 0301? 0108
$28 (&040) 0800? 0000
$2A (&042) 0001? 0100
$2C (&044) 0000? 0078
$2E (&046) 78E0? E001
$30 (&048) 0100? 0050
$32 (&050) 5000? 0018
$34 (&052) 1800? 0000
$36 (&054) 0000? .
...

Update SROM (Y/N)? y

Calculate CRC (Y/N)? y
Writing SROM from Local Buffer.....
Verifying SROM with Local Buffer...
PPC1-Bug>

Pseudo-PReP Memory Model

The following table describes the modified PowerPC Reference Platform (PReP) address map. Tornado-compatible mapping deviates only slightly from the model.

Start (CPU addr)	Size	Access to
0x0	LOCAL_MEM_SIZE (16MB min)
	DRAM
LOCAL_MEM_SIZE	(0x80000000 - LOCAL_MEM_SIZE)
	[Not used]
0x80000000	64K	PCI I/O space (16-bit)
0x80010000	8M-64K	[Not Used]
0x80800000	8M	Direct Map PCI Cfg. Space
0x81000000	1G-16M (0x3F000000)
	PCI I/O space (32-bit)
0xC0000000	1G-48M (0x3D000000)
	PCI MEM space
0xFD000000	504M (0x1F800000)
	Reserved
0xFEF80000	64K	Falcon Registers
0xFEF90000	384K	Reserved
0xFEFF0000	64K	Raven Registers
0xFF000000	8M	ROM/FLASH Bank A
0xFF800000	1M	ROM/FLASH Bank B
0xFF900000	6M	Reserved
0xFFF00000	1M	ROM/FLASH Bank A or Bank B

BOARD LAYOUT

The diagram below shows flash EEPROM locations and jumpers relevant to VxWorks configuration:

Serial port 1 (COM1) and the Ethernet port appear both on the MCPN750 and the TMCPN710 transition module. The USB ports, COM3 and COM4 headers and connectors for IDE CompactFLASH appear only on the TMCPN710 transition module.

____________________________________________________________________________
|                          Needs TMCPN710-001(002)                         |
|                          Transition Module                               |
____________________________________________________________________________
|                                                                          |
|  =========== =========== =========== ===========                         |
|                                                                          |
|  =========== =========== =========== ===========                         |
|         PMC slot                PMC slot                                 |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
| D (J7)                                                                   |
|                                                                          |
|      +-----+ +-----+                                                     |
|      |XU1  | |XU2  |                                                     |
|      |     | |     |                                                     |
|      +-----+ +-----+                                                     |
|          PPC1Bug                                                         |
|                                                                          |
|______.......................___.......................____----_____----__|
         PCI Mezzanine Card        PCI Mezzanine Card      10/100    Com1 
              Cutout                    Cutout             base T  

Key:
    U  three-pin vertical jumper, upper jumper installed
    D  three-pin vertical jumper, lower jumper installed

SEE ALSO

Tornado User's Guide: Getting Started, VxWorks Programmer's Guide: Configuration

BIBLIOGRAPHY

MCPN750 CompactPCI Single Board Computer Installation and Use, TMCPN710 Transition Module Installation and Use, Motorola MPC750 RISC Microprocessor User's Manual, Motorola PowerPC Microprocessor Family: The Programming Environments, VT82C586B PCI Peripheral Bus Controller, DECchip 21143 PCI Fast Ethernet LAN Controller Hardware Reference Manual, Peripheral Component Interconnect (PCI) Local Bus Specification, Rev 2.1, PCI to PCI Bridge Architecture Specification 2.0, PICMG 2.0 D2.14 CompactPCI Specification, Digital Semiconductor 2155x PCI-to-PCI Bridge for Embedded Applications Hardware Reference Manual, IEEE Standard 1284 Bidirectional Parallel Port Interface Specification, IEEE P1386.1 Draft 2.0 - PCI Mezzanine Card Specification (PMC), IEEE P1386 Draft 2.0 - Common Mezzanine Card Specification (CMC), SGS-Thompson MK48T59/559 CMOS 8K x 8 TIMEKEEPER SRAM Data Sheet.