VxWorks BSP Reference : mcp750
MCP750 - Motorola PowerPlus
This reference entry provides board-specific information necessary to run VxWorks. Before using a board with VxWorks, verify that the board runs in the factory configuration by using vendor-supplied ROMs and jumper settings and checking the RS-232 connection.
The Motorola PowerPlus series of boards consists of the following families: MVME230x, MVME260x, MVME360x, MVME2700, MTX60x, and MCP750. This BSP encompasses MCP750 only.
The MCP750 single-board computer is based on the PowerPC MPC750 (Arthur) microprocessors. The series part numbers are of the form:
MCP750-nnnn
where
nnnn = ECC DRAM size (DRAM contained on RAM300 module)
1222 = 16MB
1232 = 32MB
1242 = 64MB
1252 = 128MB
1262 = 256MBThe MCP750 transition module designation is TMCP700-001. The transition module contains industry standard connector access to the IEEE 1284 parallel port, a single mouse/keyboard connector, two RJ45 connectors providing access to the asynchronous serial ports configured as EIA DTE, and two HD-26 connectors providing access to the serial ports. These serial ports, labeled as Serial 3 and Serial 4 on the face plate of the TMCP700, are individually EIA-232, EIA530, V.35, or X.21 DCE or DTE requiring the installation of Motorola's Serial Interface Modules (SIMs). For more information refer to the Motorola manual <"TMCP 700 Transition Module Installation and Use">.
The BAT registers are not supported in the current cache management strategy; therefore, they can best be used for non-cacheable, data-only address regions.
The MCP750 boards have two sets of flash EEPROM (FLASH). One set of two AMD Am29F040 FLASH is socketed (sockets XU1 and XU2) and contains Motorola's s PPC1-Bug. The other set of E28f400 FLASH is soldered in. The VxWorks boot kernel resides in the soldered FLASH. See Hardware Details: ROM Considerations for information about loading and writing the boot kernel image to the soldered FLASH.These boards have non-volatile RAM; thus, boot parameters are preserved whenever the system is powered off.
To load VxWorks, and for more information, follow the instructions in the Tornado User's Guide: Getting Started.
The following jumpers are relevant to VxWorks configuration:
For details of jumper configuration, see the board diagram at the end of this entry and in the hardware manual.
MCP750 Jumper Function Description J6 ROM controller Install the jumper across pins 2 and 3 to select the socketed FLASH. Install the jumper across pins 1 and 2 to select the soldered FLASH (factory configuration). Note that ROM controller jumpers should be set to select socketed FLASH until VxWorks boot code is written to soldered FLASH, after which the jumpers should be restored to the factory configuration of soldered FLASH.
The following subsections list all supported and unsupported features, as well as any feature interaction.
The following features of the MCP750 are supported:
Feature Description Processors MPC750; 66MHz bus clock L2 Cache 1MB in-line cache, write-through only. FLASH 4MB or 8MB soldered (64-bit wide) on RAM300 mezzanine, 1MB socketed (16-bit wide). Soldered used for VxWorks boot image. DRAM 16, 32, 64, 128, 256MB, two-way interleaved; auto-sized or fixed NVRAM 8KB (MK48T59/559) 8KB Peripherals serial ports COM1 and COM2; two sync/async serial ports; AUI or 10baseT/100baseTX Ethernet interface; PS/2 floppy disk port; Primary ATA/EIDE port and Compact Flash; Secondary ATA/EIDE Port; USB ports 1 and 2 ISA Interface full 64KB memory and I/O space PCI Interface 32-bit address, 32-bit data; complies with PCI Local Bus Specification, Revision 2.1 Miscellaneous RESET switch
The board support package for the MCP750 handles automatic detection and configuration of compact PCI devices. In particular, it performs the following:
- 1)
- Probes the host PCI bridge for all devices on the host PCI bus (bus zero). Note that among the devices on bus zero might be PCI-PCI bridges. These bridges are probed as well and recursive probing occurs until all devices and bridges are found.
- 2)
- Memory is assigned to each device and sub-bridge found. For devices, each Base Address Register (BAR) is queried. Memory or I/O space (or both) is allocated for each BAR which has been implemented.
- 3)
- Complete initialization of the devices is performed, including cache Line size, command register, latency timer, interrupt line and base address registers (0 through 5). PCI-PCI bridges are initialized with the correct primary bus, secondary bus and subordinate bus designation. In short, the entire bridge/device "tree" rooted at the host pci bridge is completely configured and ready for driver access.
A new feature to the PCI autoconfiguration is "roll call". If you expect to find a certain number of specific devices identified by device/vendor ID during PCI autoconfiguration you can enter the information into a roll call list. For example assume that you know that the autoconfiguration process should find 4 different devices with device/vendor ID of 0x00461011 (this would be the Dec2155x device). You want PCI autoconfiguration to "wait" until it finds at least this many but you don't want it to wait more than 20 seconds. If 20 seconds have elapsed and 4 different Dec2155x chips have not appeared in the bus enumeration process, you would like the PCI autoconfiguration process to proceed anyway.You would construct the "roll call" list in "config.h" as shown below:
#define ROLL_CALL_MAX_DURATION 20
#define PCI_ROLL_CALL_LIST_ENTRIES \ { 4, 0x00461011 },
The parameter ROLL_CALL_MAX_DURATION specifies that no more than 20 seconds should elapse before proceeding on with the autoconfiguration, even though less than 4 Dec2155x devices have been found.
You can see the entry { 4, 0x00461011 } which says that you expect to find at least 4 devices whose device/vendor ID is 0x00461011. Note that "mcpx750.h" contains defines for some device/vendor IDs, such a define could be used here instead of a hard-coded device/vendor ID.
Also note that this list can be extended so more than one device/ vendor ID is identified with possibly a different count.
If the list is empty (except for the termination entry) then there is no roll call waiting performed, regardless of the setting of ROLL_CALL_MAX_DURATION.
The roll call feature can be useful for devices which are slow to appear on the cPCI bus. For example, MCPN750 CPU boards (which contain the Dec2155x nontransparent PCI bridge) will not be visible to an MCP750 master which is enumerating the bus until the MCPN750 clears the "primary access lock-out" bit in the Dec2155x chip control 0 register. If the MCP750's bus enumeration occurs before the MCPN750 software unlocks the Dec2155x, then the MCP750 will not know the MCPN750 is present and will not configure it. The roll call feature allows for bus enumeration polling until the specified devices actually appear. Note that roll call may not always be required for the example just presented. Some system configurations and timings may work without using the roll call feature.
The MCP750 and MPCN750 supports shared memory backplane communication. The Wind River documentation provides a great deal of information regarding shared memory concepts. The section below provides tutorial style information regarding the setup of a shared memory system involving the MCP750 and MCPN750.
Setting up a working shared memory system involves proper setting of certain "config.h" parameters and proper setting of boot parameters via the "c" command from the boot prompt. There are three components involved in shared memory communication which must be configured properly to create a working system:
The following restrictions apply to shared memory configurations.
- Anchor:
- This is an area of memory which must be accessible to all nodes participating in shared memory backplane communication. The anchor points to the actual shared memory buffer pool which must be located in the same memory space as the anchor itself. The associated "config.h" parameter is SM_ANCHOR_ADRS. In certain configurations, nonzero nodes will "poll" for the location of the anchor. "config.h" defines which comes into play for polling are SM_OFF_BOARD and SYS_SM_SYSTEM_MEM_POLL.
- Master node:
- This node is always designated as node zero. It is the node which sets up the anchor and shared memory pool. Once the anchor and shared memory pool is set up, the master node acts as a peer with the other nodes. The node number (0 in this case) is one of the boot parameters which can be set up with the "c" command from the bootline prompt.
- Sequential addressing:
- This is is governed by a "config.h" parameter, INCLUDE_SM_SEQ_ADDR and is used when sequential IP addresses are assigned to the participating nodes. Node zero is assigned the lowest IP address, followed by nodes 1, 2 etc. which are assigned the subsequent and sequential IP addresses. The advantage of sequential addressing is that fewer boot parameters must be specified to configure the system.
Note: Another piece of shared memory terminology is "host node". The "host node" is the node which configures the compact PCI bus during startup initialization. In a system consisting of an MCP750 and one or more MCPN750s, the "host node" is the MCP750. Don't confuse "host node" with "master node". "Master node" is simply a synonym for "node 0". The "host node" may or may not be the "master node". Note also that the "host node" need not necessarily be a VxWorks node.
- 1)
- Node zero must not boot over the shared memory interface. Only nonzero nodes are allowed to boot over the shared memory "sm" interface.
- 2)
- The location of the anchor must be statically determinable by the master node (node 0). That is, the location of the anchor must either be a build-time static parameter or it must be able to be communicated to the master node via the "sm=xxxxxxxx" boot configuration parameter. The nonzero nodes need not know the location of the anchor at build or boot time but can be configured to poll for the anchor dynamically.
Below are the crucial "config.h" parameters involved in shared memory:
Consider a system consisting of an MCP750 (host node) and two MCPN750s. The following six configurations are the only ones possible:
- SM_OFF_BOARD (TRUE or FALSE):
- The parameter has a configurable value of either TRUE or FALSE and directly determines the value of SM_ANCHOR_ADRS (the anchor address).
If SM_OFF_BOARD is defined as FALSE, then the anchor is on-board and SM_ANCHOR_ADRS is defined to be LOCAL_MEM_LOCAL_ADRS + SM_ANCHOR_OFFSET. LOCAL_MEM_LOCAL_ADRS is defined as 0x0 in "config.h" and SM_ANCHOR_OFFSET is defined as 0x4100 in "config.h".
If defined as TRUE, then SM_ANCHOR_ADRS is defined as a function call: sysSmAnchorAdrs( ) (defined in "sysLib.c"). This function will dynamically poll, at system startup, various locations (explained below) for the exact location of the shared memory anchor.
Note that if "sm=xxxxxxxx" is used as a boot parameter, then SM_OFF_BOARD has no effect. The value of "xxxxxxxx" will be used as the anchor location regardless of the setting of SM_OFF_BOARD. If simply "sm" is used as a boot parameter, then SM_OFF_BOARD is queried at initialization time to determine if polling is required or not.
- SYS_SM_SYSTEM_MEM_POLL (#define or #undef):
- This define only has an effect if anchor polling is called for (because SM_OFF_BOARD is defined as TRUE and "sm" is used with no "=xxxxxxxx"). In this case, simply defining SYS_SM_SYSTEM_MEM_POLL will cause the node to poll for the anchor at compact PCI bus address PCI2DRAM_BASE_ADRS + SM_ANCHOR_OFFSET (0x80004100). "System memory" (which is the host node's DRAM) will be included as one of the locations where the anchor might reside. Note that other locations my be polled as well (explained later).
Not defining SYS_SM_SYSTEM_MEM_POLL will prevent the polling of system memory for the anchor.
- SYS_SM_ANCHOR_POLL_LIST (#define or #undef):
- This define has an effect only if polling is called for (see SM_OFF_BOARD explained above). When defined, SYS_SM_ANCHOR_POLL_LIST allows a list of devices, identified by device/vendor ID and subsystem ID/subsystem vendor ID to be specified as candidates for the anchor location. Devices which appear directly on the compact PCI bus are found and if they appear on the list defined by SYS_SM_ANCHOR_POLL_LIST, they are checked to see if they house the shared memory anchor. The memory defined by the first memory BAR is queried at offset SM_ANCHOR_OFFSET (0x4100 by default, defined in "configAll.h"). If SYS_SM_ANCHOR_POLL_LIST is not defined, ALL devices on the compact PCI bus will be considered candidates for the anchor location and will be polled. If SYS_SM_ANCHOR_POLL_LIST defined but empty, NO devices on the compact PCI bus will be considered candidates for the anchor location. In that case, the only location polled would be system memory if SYS_SM_SYSTEM_MEM_POLL (see above) was defined.
- SYS_SM_DEVICE_LIST
- This define lists the Dec2155x-based cPCI boards which support shared memory by PCI Subsystem Vendor ID and Subsystem ID. To recognize a new Dec2155x-based cPCI board as a participant in the shared memory subsystem, simply add a new entry to this list.
- INCLUDE_SM_SEQ_ADDR (#define or #undef)
- If "undef'ed", sequential addressing is disabled. This symbol is defined by default.
Below is a description of how each of the above systems would be configured. Crucial "config.h" and boot parameter settings for an example system are given. In each example, SYS_SM_ANCHOR_POLL_LIST was defined to contain information identifying the Dec21554 bridge chip (present on the MCPN750). See "config.h" for the example of how this was done.
Master node on... Anchor on... Sequential Addressing? 1. MCP750 MCP750 NO 2. MCP750 MCP750 YES 3. MCPN750 MCP750 NO 4. MCPN750 MCP750 YES 5. MCPN750 MCPN750 NO 6. MCPN750 MCPN750 YES
- 1)
- MCP750 master, MCP750 anchor, no sequential addressing:
MCP750: #define SM_OFF_BOARD FALSE #undef SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : dc host name : sunray processor number : 0 inet on ethernet (e) : 124.170.16.112 inet on backplane (b): 124.200.200.1:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : gamma MCPN750-1: #define SM_OFF_BOARD TRUE #define SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : sm host name : sunray processor number : 1 inet on ethernet (e) : 124.170.16.109 inet on backplane (b): 124.200.200.2 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.1 target name (tn) : alpha MCPN750-2: (same "config.h" setup as MCPN750-1 above) boot device : sm host name : sunray processor number : 2 inet on ethernet (e) : 124.170.16.110 inet on backplane (b): 124.200.200.3 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.1 target name (tn) : beta
- 2)
- MCP750 master, MCP750 anchor, sequential addressing:
MCP750: #define SM_OFF_BOARD FALSE #define SYS_SM_CPCI_BUS_NUMBER 1 #undef SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : dc host name : sunray processor number : 0 inet on ethernet (e) : 124.170.16.112:ffffff00 inet on backplane (b): 124.200.200.1:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : gamma MCPN750-1: #define SM_OFF_BOARD TRUE #define SYS_SM_CPCI_BUS_NUMBER 1 #define SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : sm host name : sunray processor number : 1 inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : target name (tn) : alpha MCPN750-2: (same "config.h" setup as MCPN750-1 above) boot device : sm host name : sunray processor number : 2 inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : target name (tn) : beta
- 3)
- MCPN750 master, MCP750 anchor, no sequential addressing:
MCP750: #define SM_OFF_BOARD TRUE #undef SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : sm host name : sunray processor number : 1 inet on ethernet (e) : 124.170.16.112 inet on backplane (b): 124.200.200.1 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.2 target name (tn) : gamma MCPN750-1: #define SM_OFF_BOARD FALSE #define SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : dc processor number : 0 host name : sunray inet on ethernet (e) : 124.170.16.109 inet on backplane (b): 124.200.200.2:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : alpha MCPN750-2: #define SM_OFF_BOARD TRUE #define SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : sm processor number : 2 host name : sunray inet on ethernet (e) : 124.170.16.110 inet on backplane (b): 124.200.200.3 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.2 target name (tn) : beta
- 4)
- MCPN750 master, MCP750 anchor, sequential addressing:
MCP750: #define SM_OFF_BOARD TRUE #undef SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : sm processor number : 1 host name : sunray inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : target name (tn) : gamma MCPN750-1: #define SM_OFF_BOARD FALSE #define SYS_SM_CPCI_BUS_NUMBER 1 #define SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : dc processor number : 0 host name : sunray inet on ethernet (e) : 124.170.16.109:ffffff00 inet on backplane (b): 124.200.200.1:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : alpha MCPN750-2: #define SM_OFF_BOARD TRUE #define SYS_SM_CPCI_BUS_NUMBER 1 #define SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : sm processor number : 2 host name : sunray inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : target name (tn) : beta
- 5)
- MCPN750 master, MCPN750 anchor, no sequential addressing:
MCP750: #define SM_OFF_BOARD TRUE #undef SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : sm processor number : 1 host name : sunray inet on ethernet (e) : 124.170.16.112 inet on backplane (b): 124.200.200.1 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.2 user (u) : ball ftp password (pw) (blank = use rsh): flags (f) : 0x0 target name (tn) : gamma MCPN750-1: #define SM_OFF_BOARD FALSE #undef SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : dc processor number : 0 host name : sunray inet on ethernet (e) : 124.170.16.109 inet on backplane (b): 124.200.200.2:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : alpha MCPN750-2: #define SM_OFF_BOARD TRUE #undef SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : sm processor number : 2 host name : sunray inet on ethernet (e) : 124.170.16.110 inet on backplane (b): 124.200.200.3 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.2 target name (tn) : beta
- 6)
- MCPN750 master, MCPN750 anchor, sequential addressing:
MCP750: #define SM_OFF_BOARD TRUE #undef SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : sm processor number : 1 host name : sunray inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : target name (tn) : gamma MCPN750-1: #define SM_OFF_BOARD FALSE #undef SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : dc processor number : 0 host name : sunray inet on ethernet (e) : 124.170.16.109:ffffff00 inet on backplane (b): 124.200.200.1:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : alpha MCPN750-2: #define SM_OFF_BOARD TRUE #undef SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : sm processor number : 2 host name : sunray inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : flags (f) : 0x0 target name (tn) : beta
The following board features are not supported:
Feature Description DRAM ECC protection RTC MK48T59/559; only NVRAM portion is used Peripherals PS/2 keyboard port; PS/2 mouse port; IEEE1284/printer parallel port; SROM (I2C interface) ISA Interface ISA RTC PCI Interface 64-bit data; Prefetchable memory is not distinguished from nonprefetchable.
None known.
This section details device drivers and board hardware elements.
The device drivers and libraries included with this BSP:
i8250Sio - Intel 8250 UART driver (serial ports 1 and 2) z8530Sio - Zilog Z8530 SCC/Z85230 ESCC driver (serial ports 3 and 4) ppcDecTimer - PowerPC decrementer timer driver (system clock) ppcZ8536Timer - Zilog Z8536 timer driver (auxiliary and timestamp clock) ravenAuxClk - Motorola Raven timer driver for auxiliary clock ravenMpic - Motorola Raven MPIC interrupt controller driver ravenPci - Motorola Raven PCI bus bridge chip driver pciAutoConfigLib - PCI autoconfiguration library pciConfigLib - PCI configuration library pciConfigShow - Show routines of PCI bus library if_dc - 10baseT/100baseTX DEC 21140 Ethernet driver (primary LAN) byteNvRam - byte-oriented generic non-volatile RAM driver ns8730xSuperIo - National Semiconductor 8730x Super IO driver ataDrv - ATA/IDE (LOCAL and PCMCIA) disk device driver fdcDrv - floppy disk controller (FDC) Input/Output driver isaDma - DMA controller device (I8237) utilities/support driver ncr810Lib - NCR 53C825 SCSI controller library
On-board RAM for these boards always appears at address 0x0 locally.Dynamic memory sizing is supported. By default, LOCAL_MEM_AUTOSIZE is defined so memory is auto-sized at hardware initialization time. If auto-sizing is not selected, LOCAL_MEM_SIZE must be set to the actual size of DRAM memory available on the board to ensure all memory is available. The default fixed RAM size is set to 16MB (see LOCAL_MEM_SIZE in config.h).
The system interrupt vector table has 256 entries. Vectors for the various devices on the buses are assigned hierarchically as follows:
The specific ISA vector number assignments are:
Vector# Assigned to 00 - 0f ISA IRQ numbers 0 - 15 10 - 1f All MPIC interrupts 20 - 23 Raven timers 24 - 27 Raven interprocessor dispatch 28 Raven detected internal errors 29 - ff [User defined]
Vector numbers not in the table are not used by this BSP.
Vector# Assigned to 02 [Cascade interrupt from PIC2] 03 COM2 04 COM1 09 Aux timers; serial ports 3 and 4 The standard ISA Intel 8259 Programmable Interrupt Controllers (PICs) assert their interrupts through the Raven MPIC as an external interrupt. The external interrupt vector numbers are:
Vector numbers not in the table are not used by this BSP.
Vector# Assigned to 10 PBC (8259) 11 Falcon-ECC error 12 PCI Ethernet 13 PMC INT (OR of INTA# - INTD#) 14 Watchdog Timer Level 1 15 CompactPCI PRST# signal 16 CompactPCI FAL# signal 17 CompactPCI DEG# signal 18 CompactPCI Bus1 INTA# 19 CompactPCI Bus1 INTB# 1a CompactPCI Bus1 INTC# 1b CompactPCI Bus1 INTD# 1c CompactPCI Bus2 INTA# 1d CompactPCI Bus3 INTB# 1e CompactPCI Bus4 INTC# 1f CompactPCI Bus5 INTD# The Raven Multi-Processor Interrupt Controller (MPIC) sets system interrupt priorities and serves as controller of all external interrupts. Each of its 16 interrupt control registers, designated IRQ0 through IRQ15, can be programmed with a relative priority from 15, the highest, to 0, the lowest. A priority of zero effectively disables the interrupt. All but one of the 16 control registers has been hardwired to a particular interrupt source. The IRQ number and priority assignments are as follows:
For further details, refer to the appropriate board's reference guide.
Raven MPIC IRQ Priority IRQ Source IRQ0 8 PBC (8259) IRQ1 0 Falcon ECC Error IRQ2 14 Ethernet IRQ3 3 PMC INT IRQ4 0 Watchdog Timer Level 1 IRQ5 10 CompactPCI PRST# signal IRQ6 0 CompactPCI FAL# signal IRQ7 0 CompactPCI DEG# signal IRQ8 0 CompactPCI Bus 1 INTA# IRQ9 7 CompactPCI Bus 1 INTB# IRQ10 6 CompactPCI Bus 1 INTC# IRQ11 5 CompactPCI Bus 1 INTD# IRQ12 4 CompactPCI Bus 2 INTA# IRQ13 0 CompactPCI Bus 2 INTB# IRQ14 15 CompactPCI Bus 2 INTC# IRQ15 0 CompactPCI Bus 2 INTD# There are only four PCI bus interrupts: A, B, C, and D. They are shared among all PCI bus devices and do not have levels. PCI bus interrupts are wired directly to the MPIC and, therefore, have pre-assigned system vector numbers and interrupt levels. The user enables one or more PCI interrupts and connects vectored ISRs to the system by following these steps:
- 1)
- Identify the PCI interrupt letter(s) as required by the application. Based on this, identify the associated system interrupt level from the following tables:
Primary PCI Bus
----------------
A = PMC_INT_LVL1
B = PMC_INT_LVL2
C = PMC_INT_LVL3
D = PMC_INT_LVL4Secondary PCI Bus
-----------------
A = PMC_INT_LVL4
B = PMC_INT_LVL3
C = PMC_INT_LVL2
D = PMC_INT_LVL1
- 2)
- Define the vector for each PCI interrupt as follows: INT_VEC_IRQ0 + PMC_INT_LVLx where x is 1, 2, 3, or 4, as determined above.
- 3)
- In the application code, perform intConnect( ) for each vector and its associated ISR.
- 4)
- Perform IntEnable( ) for each identified system interrupt level.
- 5)
- When the application has finished, perform IntDisable( ) for each identified level.
To assist with address translation, two translation routines are provided by this BSP:
These routines accept the address space designators defined in "pci.h".
sysLocalToBusAdrs( ) Translates a local CPU address to an equivalent cPCI or local PCI memory or I/O address. sysBusToLocalAdrs( ) Translates a cPCI or local PCI memory or I/O space address to a local CPU equivalent address. Since access to the Compact PCI bus is through a transparent PCI-to-PCI bridge, the local PCI and Compact PCI busses share a common address space. As a result, the local and backpanel address designators in "pci.h" map to the same address spaces and the translation for both ranges is identical. For example, PCI_LOCAL_IO_SPACE and PCI_BACKPANEL_IO_SPACE would both reference the same address space.
Note that although there are two PCI memory spaces (normal PCI Memory space and PCI Memory I/O space), they share a single address space. In other words, PCI memory address 0x1000 cannot exist as normal PCI Memory and PCI Memory I/O simultaneously. The translation routines therefore treat both PCI Memory and PCI Memory I/O as a single address space.
The MCP750 has four serial ports. All are ISA bus devices. Two, serial port 1 (COM1 or console) and serial port 2 (COM2), originate from the PC87308 Super I/O (SIO) chip. The SIO serial ports are functional equivalents to those in an Intel 8250 UART.The other two serial ports are serial ports 3 and 4. All but the DTR and DSR lines for these ports are implemented in the Zilog Z85230 ESCC chip. The DTR and DSR lines for serial ports 3 and 4 are implemented in the Zilog Z8536 CIO chip. Serial ports 3 and 4 can be configured as synchronous serial ports but no support for this mode is provided by this BSP.
By default, all serial ports are configured as asynchronous, 9600 baud, with 1 start bit, 8 data bits, 1 stop bit, no parity, and no hardware handshake. Hardware handshake using RTS/CTS is a supported option on all ports.
The MCP750 transition module has two RJ-45 connectors for COM1 and COM2; these are permanently configured as DTE. Serial ports 3 and 4 have special HD-26 connectors and require Serial Interface Modules (SIMs) that come configured as DCE or DTE versions of EIA-232, EIA-530, X.21 or V.35. For details, consult TMCP 700 Transition Module Installation and Use.
All boards have one Ethernet port which is 10baseT and 100baseTX compatible.The MCP750 uses an RJ45 (twisted pair) jack and can be used with either 10baseT or 100baseTX. The Ethernet driver automatically senses and configures the port as 10baseT or 100baseTX. The Ethernet driver is compatible with DEC21040, DEC21140, and DEC21143 devices.
The Media Access Control (Ethernet) address for each port is obtained from a serial ROM contained in the DEC21140 chip. If the address is not found in serial ROM, the driver attempts to read it from NVRAM at offset 0x202c.
Compact Flash is supported on the MCP750 as IDE controller 0, device 0. To configure the compact flash, perform the following:
- 1)
- In config.h, replace "#undef INCLUDE_ATA" with "#define INCLUDE_ATA".
- 2)
- Make sure that the ATA_DEV0_STATE line reads:
#define ATA_DEV0_STATE DEV_PRESENT- 3)
- Rebuild the kernel. After booting, the compact flash device can be configured with the following command:
usrAtaConfig(0,0,"/ata0")
A PC-compatible floppy disk is supported on the MCP750 via a PS/2 connector on the TMCP700 transition module. To configure the floppy disk, perform the following:
- 1)
- In config.h, replace "#undef INCLUDE_FD" with "#define INCLUDE_FD".
- 2)
- If a DOS file system is needed, #define INCLUDE_DOSFS in config.h.
- 3)
- Rebuild the kernel. After booting, the floppy disk can be accessed as a raw device and/or a DOS file system disk if INCLUDE_DOSFS was defined.
Refer to the VxWorks Programmer's Guide, section 4.2 for information on the DOS file system, its configuration, and use.
Two USB ports are supported on the MCP750. They are located on the front panel as J17 and J18, and can be re-routed to the optional transition module TMCP700. The USB controller is inside the PCI Peripheral Bus Controller (PBC) on the MCP750 and is HCI v1.1 compatible.The USB Developer Kit for Tornado is available as an optional product. It includes a USB stack for VxWorks, as well as drivers for various types of USB peripherals. Detailed information can be obtained from the USB Developer Kit documentation.
To enable PCI auto configuration of the USB device, the file sysBusPci.c needs to be modified. In sysPciAutoConfigInclude( ), the case PCI_ID_USB in switch(devVend) should be changed to return OK instead of ERROR. After this change, rebuild and flash a new bootrom by following the instructions in the "ROM Considerations" section. After verifying the new bootrom is functioning properly, proceed to the USB Developer Kit documentation.
The supported boot device is:dc - Ethernet (10baseT or 100baseTX or AUI)
Motorola's PPC1-Bug can be used to download and run VxWorks. Consult the user's manuals for details.
The boot methods are affected by the boot parameters. If no password is specified, RSH (remote shell) protocol is used. If a password is specified, FTP protocol is used, or, if the flag is set, TFTP protocol is used.
Use the following command sequence on the host to re-make the BSP boot ROM:cd target/config/mcp750 make clean make bootrom.bin chmod 666 bootrom.bin cp bootrom.bin /tftpboot/bootrom.binPower down the board and switch the ROM jumper to select socketed FLASH. Connect the Ethernet and console serial port cables, then power the board back up.
At the PPC1-Bug prompt, set up the network transfer from a TFTP host using niot. Important: You must have a TFTP server running on your host's subnet for the niop command to succeed. Using niot, the Client IP Address, Server IP Address, and Gateway IP Address must be set up for the user's specific environment:
PPC1-Bug>niot Controller LUN =00? Device LUN =00? Node Control Memory Address =00FA0000? Client IP Address =123.123.10.100? 123.321.12.123 Server IP Address =123.123.18.105? 123.321.21.100 Subnet IP Address Mask =255.255.255.0? Broadcast IP Address =255.255.255.255? Gateway IP Address =123.123.10.254? 123.321.12.254 Boot File Name ("NULL" for None) =? . Update Non-Volatile RAM (Y/N)? y PPC1-Bug>The file is transferred from the TFTP host to the target board using the niop command. The file name must be set to the location of the binary file on the TFTP host. The binary file must be stored in the directory identified for TFTP accesses, but the file name is a relative path and does not include the /tftpboot directory name:
PPC1-Bug>niop Controller LUN =00? Device LUN =00? Get/Put =G? File Name =? bootrom.bin Memory Address =00004000? Length =00000000? Byte Offset =00000000? PPC1-Bug>After the file is loaded onto the target, the pflash command is used to put it into soldered FLASH parts.
PPC1-Bug>pflash 4000:FFF00 ff000100When the command is finished, power down the board and switch the ROM jumper to select soldered FLASH. Then power the board back up.
This section describes miscellaneous information concerning this BSP and its use.
The delivered objects are: bootrom, bootrom.hex, vxWorks, vxWorks.sym, and vxWorks.st.
The make targets are listed as the names of object-format files. Append .hex to each to derive a hex-format file name, or .bin to each to derive a binary format file name.
Note, "bootrom_res", "vxWorks.res_rom", and "vxWorks.res_rom_nosym" are also make targets but are not part of the PowerPC supported set. These particular targets will not build in the PowerPC environment.
bootrom bootrom_uncmp bootrom_res_high vxWorks (with vxWorks.sym) vxWorks.st vxWorks_rom vxWorks.st_rom vxWorks.res_rom_res_low (builds but does not execute) vxWorks.res_rom_nosym_res_low (builds but does not execute)
For these boards, the value of the CPU clock speed is read from the CPU configuration register using the macro MEMORY_BUS_SPEED which is defined in mcpx750.h. For example:
clkFreqMhz = MEMORY_BUS_SPEED;
MCP750 boards prior to REV D have a hardware problem in which ISA interrupts which are supposed to be level sensitive do not function properly. The software automatically detects such boards and configures the ISA interrupts for edge sensitivity instead of level sensitivity. This allows the serial ports to function on pre-REV D boards. A side effect of the problem however, is that that a serial port, under a heavy load, may hang due to a missed interrupt. Boards which are REV D and later have had their hardware modified to allow the ISA interrupts to properly function in level mode and the software will detect this and perform the necessary programming to respond to level sensitive interrupts. REV D and later boards will not experience serial port hangs due to edge/level sensitivity problems.
To determine if the board is REV D or later, refer to the circuit board number which is printed on the back side of the board, near the front panel USB 0 port opening. The number is etched into the copper. A number such as "01-W3288F01C" will appear. The last character ("C" in this example) will indicate the revision level.
- 1)
- The serial port (console) appears to work fine, but it does lock up while running the Wind River Validation Test Suite.
- 2)
- The routine ataShow does not display the information for the secondary ATA controller when devices are attached to it. The devices function properly though, it is just the ataShow routine that has problems.
The following table describes the modified PowerPC Reference Platform (PReP) address map. Tornado-compatible mapping deviates only slightly from the model.
Start (CPU addr) Size Access to 0x0 LOCAL_MEM_SIZE (16MB min) DRAM LOCAL_MEM_SIZE (0x80000000 - LOCAL_MEM_SIZE) [Not used] 0x80000000 64K PCI I/O space (16-bit) 0x80010000 8M-64K [Not Used] 0x80800000 8M Direct Map PCI Cfg. Space 0x81000000 1G-16M (0x3F000000) PCI I/O space (32-bit) 0xC0000000 1G-48M (0x3D000000) PCI MEM space 0xFD000000 504M (0x1F800000) Reserved 0xFEF80000 64K Falcon Registers 0xFEF90000 384K Reserved 0xFEFF0000 64K Raven Registers 0xFF000000 8M ROM/FLASH Bank A 0xFF800000 1M ROM/FLASH Bank B 0xFF900000 6M Reserved 0xFFF00000 1M ROM/FLASH Bank A or Bank B
The diagram below shows flash EEPROM locations and jumpers relevant to VxWorks configuration:
Serial ports 1 and 2, the Ethernet port, and the two USB ports appear both on the MCP750 and the TMCP700-001 transition module. The parallel port, serial ports 3 and 4, and the keyboard/mouse port appear only on the TMCP700-001 transition module.
____________________________________________________________________________ | Needs TMCP700-001 | | Transition Module | ____________________________________________________________________________ | ...............................................| | ========== ========== . .| | . ============== (Compact Flash) .| | ========== ========== . .| | PMC slot . .| | . .| | . RAM300 DRAM mezzanine board .| | . ...............| | . . | | . . | | . . | | . . | | . +----+ . | | . | |<== (PPC1Bug) . | | . | | . | | . +----+ . | | . (XU1) . | | . +----+ . | |D J6 . | | . | | . | | . | | . +----+ . | | . (XU2) . | | . . | | ................................. | |__........................___----____----_______________________---__---__| 10/100 Com1 USB USB Base T 1 2Key:
U three-pin vertical jumper, upper jumper installed
D three-pin vertical jumper, lower jumper installed
() Features labeled in parentheses are below the mezzanine board.
Tornado User's Guide: Getting Started, VxWorks Programmer's Guide: Configuration
MCP 750 CompactPCI Single Board Computer Installation and Use, TMCP 700 Transition Module Installation and Use, Motorola MPC750 RISC Microprocessor User's Manual, Motorola PowerPC Microprocessor Family: The Programming Environments, VT82C586B PCI Peripheral Bus Controller, DECchip 21140 PCI Fast Ethernet LAN Controller Hardware Reference Manual, PC87307VUL Super I/O Device Data Manual, Zilog SCC (Serial Communications Controller) User's Manual, Zilog ZCIO Counter/Timer and Parallel I/O Unit User's Manual, Peripheral Component Interconnect (PCI) Local Bus Specification, Rev 2.1, PCI to PCI Bridge Architecture Specification 2.0, PICMG 2.0 D2.14 CompactPCI Specification, IEEE Standard 1284 Bidirectional Parallel Port Interface Specification, IEEE P1386.1 Draft 2.0 - PCI Mezzanine Card Specification (PMC), IEEE P1386 Draft 2.0 - Common Mezzanine Card Specification (CMC), SGS-Thompson MK48T59/559 CMOS 8K x 8 TIMEKEEPER SRAM Data Sheet.