LoPEC - Motorola
This manual entry covers the BSP for VxWorks running on the LoPEC board. It provides board-specific information necessary to run VxWorks. Before using a board with VxWorks, verify that the board runs in the factory configuration by using vendor-supplied ROMs and DIP switch settings and checking the serial connection. This BSP is compatible with Wind River's Tornado 2 development environment.
The LoPEC board is a single-board computer based on the PowerPC MPC750 or MPC7410 microprocessor and using the MPC107 PCI bridge/memory controller.
The LoPEC boards have two sets of flash EEPROM (FLASH). Bank 0 consists of two 32-pin PLCC sockets which can be populated with up to 1024KB of FLASH memory. Bank 0 resides at address 0xFFF00000 and is restricted to 8 bits in width. This memory contains Motorola's PPC5-Bug. Bank 1 is populated with four 512Kx16 FLASH devices to obtain 4MB of 64-bit wide expansion FLASH memory or four 1Mx16 FLASH devices to obtain 8MB of 64-bit wide FLASH memory. The expansion FLASH memory starts at address 0xFF000000 and is soldered onto the board. The VxWorks bootrom image can be programmed ("pflash'ed") into the soldered Bank 1. See Hardware Details: ROM Considerations for information about loading and writing the boot kernel image to the soldered FLASH.These boards have non-volatile RAM; thus, boot parameters are preserved whenever the system is powered off.
To load VxWorks, and for more information, follow the instructions in the Tornado User's Guide: Getting Started.
The following DIP switch is relevant to VxWorks configuration:
Switch Function Description S1[0] ROM Selection This switch is located on the bank of 8 DIP switches and occupies the position closest to the edge of the board. To run from socketed flash-ROM the switch must be pushed toward the processor (refer to diagram at the end of this document). To run from soldered flash-ROM the switch must be pushed away from the processor. Normally PPC5-Bug will reside in the socketed flash-ROM and the VxWorks bootrom image will reside in soldered flash-ROM. See "ROM considerations" for a complete description of this.
The following subsections list all supported and unsupported features, as well as any feature interaction.
The following features of the LoPEC board are supported:
Feature Description Processor MPC750 and MPC7410; 66.67 and 100 MHz bus clock FLASH 1MB socketed (8-bit wide); 4 or 8MB expansion (4x16-bit wide) Memory 32MB to 1GB ECC PC100 Synchronous DRAM (SDRAM); CHRP memory model (MPC107 Memory Map B); L1 and L2 cache NVRAM 32KB (MK48T37) RTC, Alarm Clock, and Failsafe Timer MK48T37 Peripherals Three 16550-compatible async serial ports; Intel 82559 10/100Base-TX Ethernet interface; ATA-33 3.5 inch Disk EIDE Port; Type 2 IDE Compact Flash Port or 2.5 inch Disk EIDE Port; Ultra2 SCSI - SYM53C895A; On-board fail LED PCI Interface One 32-bit PCI slot. Two PMC sites, signal wide, 33MHz, 32 bit.
The following features of the LoPEC board are not supported:
Feature PrEP Memory Model (MPC107 Memory Map A) Parallel port interface USB interface Driver for programming flash banks True Flash File System Abort switch MPC107 DMA MPC107 Power Management Facilities MPC107 I20 Messaging MPC107 EPIC timers 1-3
None known.
This section details device drivers and board hardware elements.
The device drivers and libraries included with this BSP are:
Driver name Description i8250Sio Intel 8250 (or 16550 compatible) UART driver (serial port) ppcDecTimer PowerPC decrementer timer driver (system clock) byteNvRam byte-oriented generic non-volatile RAM driver mpc107Epic Motorola MPC107 EPIC interrupt controller driver mpc107AuxClk Motorola MPC107 auxiliary clock library sysI2cMpc107 Motorola MPC107 I2C serial EEPROM driver sysIbc PIB interrupt controller driver (Winbond W83c554) pciConfigLib PCI configuration library sysI2cDrv MPC107 I2C interface driver sysMotVpd Vital Product Data support sysMotVpdUtil Vital Product Data Utility routines ataDrv ATA/IDE (LOCAL and PCMCIA) disk device driver m48t37 STMicroelectronics M48T37 Timekeeper SRAM device driver sysRtc Real-Time Clock and Alarm Clock support routines sysFailsafe Failsafe (watchdog) Timer support routines
This BSP supports the END (Enhanced Network Driver) as the only network interface for Tornado 2.
On-board RAM for these boards always appears at address 0x0 locally.Dynamic memory sizing is supported in this BSP release. It is controlled by the LOCAL_MEM_AUTOSIZE define in config.h.
The LoPEC supports one memory mapping, the CHRP memory map (MPC107 Memory Map B), which is described in the next section.
The following tables describe the CHRP address mappings, also referred to as MPC107 "Memory Map B". "Memory Map B" is the only memory map supported by this BSP. Most of the address maps are fixed by hardware and the base addresses cannot be modified by the user. Note that the BSP does not make available all of the PCI space documented below. Instead, an adjustable set of #define's in lopec.h and config.h specify how much space in the PCI memory map is actually useable. See sysBusPci.c for a memory map of what is actually available.
Table I. CHRP Map From CPU Point of View. Processor Address Size Access to 0x00000000 LOCAL_MEM_SIZE (32MB min) DRAM LOCAL_MEM_SIZE (0x40000000 - LOCAL_MEM_SIZE) Unused DRAM space 0x40000000 1GB Reserved 0x80000000 2GB-32MB (0x7e000000) PCI Memory space 0xFE000000 64KB PCI 16-bit I/O (ISA) space (*1) 0xFE010000 8MB-64KB (0x007f0000) Reserved (*1) 0xFE800000 4MB PCI 32-bit I/O space (*1) 0xFEC00000 2MB PCI Configuration Addr Reg. 0xFEE00000 1MB PCI Configuration Data Reg. 0xFEF00000 1MB PCI interrupt Ack. 0xFF000000 8MB 64 bit soldered FLASH/ROM 0xFFF00000 1MB 8 bit socketed FLASH/ROM
Table II. PCI Memory Space Access PCI Address Size Access to 0x00000000 1GB (max) DRAM space 0x40000000 1GB (fixed) Reserved (not addressable by processor) 0x80000000 2GB-32MB (0x7e000000) PCI MEM space 0xFE000000 32MB Reserved (not addressable by processor)
Table III. PCI I/O Space Access I/O Bus Address Size Access to 0x00000000 64KB 16-bit I/O (ISA) space 0x00010000 8MB-64KB (0x007f0000) Reserved 0x00800000 4MB 32-bit I/O space 0x00C00000 4GB-12MB Reserved (Not addressable by processor)
Shared memory is a concept that works in a common backplane configuration and is not supported on this board.
The system interrupt vector table has 256 entries. Vectors for the various devices on the buses are assigned hierarchically as follows:
Vector# Assigned to 0x00 - 0x0f ISA interrupts 0x10 - 0x1f MPC107 Epic serial interrupts 0x20 - 0x23 MPC107 Epic timer interrupts (*) 0x24 - 0x26 MPC107 Epic internal interrupts (*) 0x27 - 0x47 MPC107 Message Unit Doorbell interrupts (*) 0x48 - 0xff [User defined] The specific ISA vector number assignments are:
Vector/IRQ# Assigned to 00 Timer 1/Counter 0 (*) 01 Legacy Keyboard IRQ from USB controller (*) 02 [Cascade interrupt from PIC2] 03 Reserved 04 Reserved 05 Reserved 06 Reserved 07 Legacy Mouse IRQ from USB controller (*) 08 Reserved 09 Reserved 10 Reserved 11 Reserved 12 Legacy Mouse IRQ from USB controller (*) 13 ISA DMA complete (*) 14 Primary IDE interrupt 15 Secondary IDE interrupt The Embedded Programmable Interrupt Controller (EPIC) sets system interrupt priorities and serves as controller of all external interrupts. Each of its 16 interrupt control registers can be programmed with a relative priority from 15, the highest, to 0, the lowest. A priority of zero effectively disables the interrupt. All of the 16 control registers have been hard-wired to a particular interrupt source. The EPIC interrupt controller will operate in the serial interrupt mode.
The external interrupt vector numbers and priority assignments are:
EPIC IRQ# Vector# EPIC Priority Interrupt Source 0x0 0x10 0x3 PIB (EIDE) 0x1 0x11 0x14 i82559 Ethernet Controller 0x2 0x12 0x0 Unused 0x3 0x13 0x0 Unused 0x4 0x14 0x8 X-port COM 2 0x5 0x15 0x8 X-port COM 3 0x6 0x16 0x3 SCSI controller 0x7 0x17 0x13 PCI Expansion Interrupt 1 (a) 0x8 0x18 0x13 PCI Expansion Interrupt 2 (b) 0x9 0x19 0x13 PCI Expansion Interrupt 3 (c) 0xa 0x1a 0x13 PCI Expansion Interrupt 4 (d) 0xb 0x1b 0x3 USB Host Controller (*) 0xc 0x1c 0x0 Peripheral Parallel Controller (*) 0xd 0x1d 0x8 X-port COM 1 0xe 0x1e 0x4 Abort Switch (*) 0xf 0x1f 0x5 RTC/IRQ
The 32-bit PCI bus is fully supported under the PCI Local Bus Specification, Revision 2.1. The 64-bit extensions are not supported. All configuration space accesses are made with BDF (bus number, device number, function number) format calls in the pciConfigLib module. To simplify the addition of PCI-based add-in cards, the BSP provides a PCI auto-configuration library. The BSP will automatically locate and configure installed PCI devices. This configuration, performed during initialization immediately after power-up programs PCI memory BARs, interrupt lines, and other appropriate PCI configuration information for all PCI devices. The starting addresses and extents of PCI spaces are documented in sysBusPci.c.
The BSP provides support for all three types of memory error detection and correction: 0 (no parity), 1 (normal and RMW parity as well as ECC), and 2 (RMW parity and ECC). When type 0 memory is detected, the MPC107 PCI Bridge/Memory Controller is configured for no parity or ECC, regardless of the setting of INCLUDE_ECC. If type 1 or 2 memory is detected and INCLUDE_ECC is not defined, the memory controller is configured for RMW parity. If type 1 or 2 memory is detected and INCLUDE_ECC is defined, the memory controller is configured for ECC.When ECC is enabled, single-bit errors are detected and corrected but neither single-bit nor multiple-bit errors are reported. The MPC107 reports single-bit and multiple-bit errors by asserting the machine check signal to the processor. In order to enable ECC you must replace the "#undef INCLUDE_ECC", in config.h, with "#define INCLUDE_ECC", and rebuild the bootrom and kernel.
The three serial ports on the LoPEC board family are implemented as SCC 16550 UARTS. The RJ-45 jack is placed as an edge connector on the board and is configured as a DTE connection. It serves as the COM1 interface. The COM2/3 interfaces are implemented as two ten-pin headers labeled J29 and J30 (see diagram at the end of this document).By default, the serial port is configured as asynchronous, 9600 baud, with 1 start bit, 8 data bits, 1 stop bit, no parity, and no hardware or software handshake. Hardware handshake using RTS/CTS is a supported option.
SCSI is supported on the LoPEC through the Symbios/LSI Logic SYM53C895A PCI to Ultra2 SCSI controller. To enable SCSI you must replace the "#undef INCLUDE_SCSI", in config.h, with "#define INCLUDE_SCSI", and rebuild the bootrom and kernel.The following defines are used to configure SCSI support, and can also be found in config.h:
Define Description INCLUDE_SCSI_BOOT Enables booting from a SCSI device. It is defined by default. INCLUDE_DOSFS Enables DOS file system support. It is defined by default. SCSI_AUTO_CONFIG Enables an automatic scan of the SCSI bus at startup. It is undefined by default. SYS_SCSI_CONFIG Enables you to declare a SCSI peripheral configuration, and is meant as a substitute for SCSI_AUTO_CONFIG. You must also edit sysScsiConfig in sysScsi.c, so that it reflects the actual configuration of your SCSI bus. It is undefined by default.
- 1)
- To configure unformatted SCSI hard drives you use the following commands:
If SCSI_AUTO_CONFIG is not defined in config.h, substitute ID and LUN with the SCSI ID and logical unit number for your SCSI drive, and execute the following to format and mount the scsi drive:
pPhysDev0 = scsiPhysDevCreate(pSysScsiCtrl,<ID>,<LUN>,0,-1,0,0,0) pBlkDev0 = scsiBlkDevCreate(pPhysDev0, 0, 0) pDosVolDesc = dosFsMkfs ("/sd0", pBlkDev0)If SCSI_AUTO_CONFIG is defined in config.h, execute the following at the vxWorks kernel prompt:Type "scsiShow" at the kernel prompt, which will display the following: ID LUN VendorID ProductID Rev. Type Blocks BlkSize pScsiPhysDev -------------------------------------------------------------------------- 0 0 SEAGATE ST11200N ST31230 0660 0 2069860 512 0x01fcb4dc 1 0 SEAGATE ST12400N ST32171 0460 0 4194158 512 0x01fc9a50 Next, using the pScsiPhysDev value from the resulting table, execute the following commands: pBlkDev0 = scsiBlkDevCreate(pScsiPhysDev, 0, 0) pDosVolDesc = dosFsMkfs("/sd0",pBlkDev0)- 2)
- To configure formatted SCSI hard drives you use the following commands:
Type "scsiShow" at the kernel prompt, which will display the following: ID LUN VendorID ProductID Rev. Type Blocks BlkSize pScsiPhysDev -------------------------------------------------------------------------- 0 0 SEAGATE ST11200N ST31230 0660 0 2069860 512 0x01fcb4dc 1 0 SEAGATE ST12400N ST32171 0460 0 4194158 512 0x01fc9a50 Next, using the pScsiPhysDev value from the resulting table, execute the following commands: pBlkDev0 = scsiBlkDevCreate(pScsiPhysDev, 0, 0) pDosVolDesc = dosFsDevInit("/sd0",pBlkDev0, -1)
All boards have one Ethernet port which is 10baseT and 100baseTX compatible. The port is implemented as an RJ45 edge connector.The Ethernet driver automatically senses and configures the port as 10baseT or 100baseTX.
The Media Access Control (Ethernet) address for each port is obtained from a serial ROM contained in the i82559 chip. If the address is not found in serial ROM, the driver attempts to read it from NVRAM.
Compact Flash is supported on the LoPEC as IDE controller 1, device 0. Once you have a Compact Flash device installed, you will need to configure it by performing the following:
- 1)
- In config.h, replace "#undef INCLUDE_ATA" with "#define INCLUDE_ATA".
- 2)
- Make sure that the ATA_DEV2_STATE line reads:
#define ATA_DEV2_STATE DEV_PRESENT- 3)
- Rebuild the kernel. After booting, the Compact Flash device can be configured with the following command:
If a dosFs file system has never been set up on the device:
pDisk = ataDevCreate(1,0,0,0) pAtaVol = dosFsMkfs("/ata2",pDisk)ORIf a dosFs file system has previously been set up on the device:
usrAtaConfig(1,0,"/ata2")
ATA-33 3.5 inch disk EIDE is supported on the LoPEC as IDE controller 0, device 0 for the master device, and device 1 for the slave device. 2.5 inch disk EIDE is supported as IDE controller 0, device 0 for the master device, and device 1 for the slave device. The 3.5 inch and 2.5 inch EIDE header cannot be populated at the same time. Once you have an EIDE disk installed you will need to configure it by performing the following:
- 1)
- In config.h, replace "#undef INCLUDE_ATA" with "#define INCLUDE_ATA".
- 2)
- Make sure that the appropriate ATA_DEVn_STATE is set to DEV_PRESENT:
#define ATA_DEV0_STATE DEV_PRESENT /* 3.5/2.5 inch master device */ #define ATA_DEV1_STATE DEV_PRESENT /* 3.5/2.5 inch slave device */- 3)
- Rebuild the kernel. After booting, the EIDE disks can be configured with the following commands:
If a dosFs file system has never been set up on the device:
pDisk = ataDevCreate(<controller#>,<device#>,<#ofblocks>,<blockoffset>) pAtaVol = dosFsMkfs("<mountpoint>",pDisk)ORIf a dosFs file system has previously been set up on the device:
usrAtaConfig(<controller#>,<device#>,"/ata<#>")For example, to set up a dosFs file system on a 3.5 inch master device you would use the following commands:
pDisk = ataDevCreate(0,0,0,0) pAtaVol = dosFsMkfs("/ata0",pDisk)
Support for a failsafe ( ie. watchdog ) timer is provided. The failsafe timer is implemented with the STMicroelectronics M48T37Y Timekeeper SRAM. This support is not part of the standard VxWorks watchdog library, wdLib. Failsafe timer expiration can be reported via a maskable interrupt or via a board reset event. The timeout lengths range from 0 (disable) to 31 seconds.
Failsafe timer support can be included in the BSP by defining INCLUDE_FAILSAFE in config.h. This support by default is excluded. There is only one failsafe timer on the board, so only one failsafe timer can be established at any given time.
The failsafe timer is disabled at power-up and after a reset. The failsafe timer support routines are defined in sysFailsafe.c.
In order to use the failsafe timer, the user will need to first call sysFailsafeSet( ). The routine takes as parameters the number of seconds until expiration and whether or not to generate a board reset upon expiration. If reset is set to FALSE, an interrupt occurs, if reset is set to TRUE, a board reset occurs. Passing a value of 0 for seconds will disable the failsafe timer. Once the timer has been set, subsequent calls to sysFailsafeSet( ) will extend the timer for the specified number of seconds.
A call to sysFailsafeCausedReset( ) will determine whether the failsafe timer caused the last board reset. This information will be lost if a call to sysAlarmSet( ) is made prior to calling sysFailsafeCausedReset( ).
A call to sysFailsafeCancel( ) will disable the failsafe timer. The current failsafe timer settings can be retrieved with a call to sysFailsafeGet( ). The current failsafe timer settings can be displayed with a call to sysFailsafeShow( ), this displays the current settings not the number of seconds until timer expiration. The routine sysFailsafeIntr( ) is the failsafe timer interrupt handler. In order to define your own interrupt handler, simply edit this routine.
Support for a real-time clock and an alarm clock are provided. The real-time and alarm clocks are implemented with the STMicroelectronics M48T37Y Timekeeper SRAM.
Real-time and alarm clock support are included in the BSP by defining INCLUDE_RTC in config.h. This support by default is excluded.
When the real-time clock information matches the alarm clock settings an interrupt will be generated.
Once set, the alarm clock will retain its settings upon a board reset. The real-time and alarm clock support routines are defined in sysRtc.c.
The real-time clock can be set with a call to sysRtcSet( ). The following information needs to be supplied in order to set the RTC: century, year, month, day of month, day of week, hour, minute, and second. The current RTC settings can be retrieved with a call to sysRtcGet( ). The current RTC date and time can be displayed with a call to sysRtcShow( ). The sysRtcDateTimeHook( ) routine is provided as a hook to the vxWorks dosFsLib as a means of providing the date and time for file timestamps.
The alarm clock can be programmed in the following five ways:
Method Configurable Parameters ------------------------------------------------------------ Once a month Date, hour, minute, second Once a day Hour, minute, second Once an hour Minute, second Once a minute Second Once a second (none)The alarm clock is set with a call to sysAlarmSet( ). This routine takes a method and the alarm clock parameters as arguments. The alarm clock can be cancelled with a call to sysAlarmCancel( ). The current alarm clock settings can be retrieved with a call to sysAlarmGet( ). The current alarm clock settings can be displayed with a call to sysAlarmShow( ). The routine sysAlarmIntr( ) is the alarm clock interrupt handler. In order to define your own interrupt handler, simply edit this routine.
The supported boot devices are:fei - Ethernet (10baseT or 100baseTX) scsi=<scsi_id#>,<lun#> - SCSI Drive ata=<controller number>,<device number> - ATA/IDE Drive controller number is: 0 = 3.5" or 2.5" master/slave device 1 = Compact Flash device (master only) device number is: 0 = 3.5" master device or 2.5" master device or Compact Flash device 1 = 3.5" slave device or 2.5" slave deviceNote: By default, with INCLUDE_ATA defined, vxWorks is not set up for any
devices. If you have multiple controllers and/or hard disks you must
modify the ATA_DEVn_STATE defines in config.h to support more drives.
The boot methods are affected by the boot parameters. If no password is specified, RSH (remote shell) protocol is used. If a password is specified, FTP protocol is used, or, if the flag is set, TFTP protocol is used.These protocols are used for Ethernet interface.
LoPEC contains both socketed and soldered flash ROMs.
Socketed flash-ROM appears at address 0xFFF00000.
Soldered flash-ROM appears at address 0xFF000000.
Execution on power-up always begins at 0xFFF00100. Thus a functioning board must always have socketed ROM installed at power-up.
The determination as to whether or not to continue to execute out of socketed flash-ROM or to jump to soldered flash-ROM (0xFF000100) is controlled by a bit in the configuration header register (1-byte at address 0xFFE04000) which represents the setting of DIP switch zero. If the DIP switch is on, the start-up code will jump to soldered flash-ROM (0xFF000100), if it is off start-up code will continue to execute out of socketed flash-ROM (0xFFF00100).
Note that the DIP switches are not labeled with numbers. The diagram that appears later in this section describes the location of the DIP switch which controls the ROM boot. The other DIP switches in the bank of 8 have no effect on any VxWorks functions.
The state of FLASH_BOOT (#define or #undef) in "config.h" must be set based upon which type of flash-ROM (soldered or socketed) is to hold the VxWorks bootrom image.
The default state is for FLASH_BOOT to be #define'd. This produces a VxWorks bootrom which will only run out of soldered flash-ROM. Since PPC5-Bug runs out of socketed ROM, this makes management of the VxWorks bootrom convenient (the VxWorks bootrom can be download and "pflash"ed into soldered flash-ROM with PPC5-Bug).
It is also possible to #undef FLASH_BOOT and rebuild the VxWorks bootrom image. This would create an image which will only run out of socketed ROM. Although this is a possible configuration, it is not as convenient since the PPC5-Bug will only run out of socketed flash-ROM and placing the VxWorks bootrom image into socketed flash-ROM causes complete loss of PPC5-Bug.
Note that PPC5-Bug has been built to run only out of socketed-ROM. Attempting to move the PPC5-Bug from socketed flash-ROM to soldered flash-ROM via the "pflash" command will result in a non-functioning PPC5-Bug.
X X X X X X X | S1 | | | | | | | | | | | | | | | X <-- This is the DIP switch which controls whether we are running from socketed (processor side) or soldered flash. Set in this position we are running from socketed flash (which contains PPC5-Bug). This DIP switch is closest to the edge of the board. Here is how the DIP switches looked when running from soldered flash, again remember that the board is oriented in such a way that the processor is closest to us. X X X X X X X X <-- Note we have moved this switch. S1 | | | | | | | | | | | | | | | | (processor side) The remaining DIP switches play no role in the ROM selection processed and their positioning is irrelevant. Use the following command sequence on the host to re-make the BSP boot ROM: cd target/config/lopec make clean make bootrom.bin chmod 666 bootrom.bin cp bootrom.bin /tftpboot
Before you power-up the LoPEC, make sure the DIP switch which selects socketed flash-ROM or soldered flash-ROM (described above) is properly set so that PPC5-Bug runs.
At the PPC5-Bug prompt, start the system clock then set up the network transfer from a TFTP host using niot. To start the system clock, the set command must be used. The format is: set MMDDYYhhmm where MM is month, DD is day of month, YY is year, hh is hour (24-hour format), and mm is minutes. This command starts the system clock and sets the current date and time.
PPC5-Bug>set 1016971302Using niot, the Client IP Address, Server IP Address, and Gateway IP Address must be set up for the user's specific environment:
PPC5-Bug>niot Controller LUN =00? Device LUN =00? Node Control Memory Address =00FA0000? Client IP Address =123.123.10.100? 123.213.12.123 Server IP Address =123.123.18.105? 123.213.21.100 Subnet IP Address Mask =255.255.255.0? Broadcast IP Address =255.255.255.255? Gateway IP Address =123.123.10.254? 123.213.12.254 Boot File Name ("NULL" for None) =? . Update Non-Volatile RAM (Y/N)? y PPC5-Bug>The file is transferred from the TFTP host to the target board using the niop command. Important: You must have a TFTP server running on your host's subnet for the niop command to succeed. The file name must be set to the location of the binary file on the TFTP host. The binary file must be stored in the directory identified for TFTP accesses, but the file name is a relative path and does not include the /tftpboot directory name:
PPC5-Bug>niop Controller LUN =00? Device LUN =00? Get/Put =G? File Name =? boot.bin Memory Address =00004000? Length =00000000? Byte Offset =00000000? PPC5-Bug>After the file is loaded onto the target, the "pflash" command is used to put it into soldered flash-ROM:To put it into soldered FLASH:
PPC5-Bug>pflash 4000:fff00 ff000100When the command is finished, power down the board, move the DIP switch, then power the board back up.The value of FLASH_BOOT in config.h must be set appropriately for the VxWorks bootrom image being flashed, otherwise the bootrom will not execute. See ROM Considerations for more details on setting up FLASH_BOOT correctly. Also note that PPC5-Bug has been compiled to run out of socketed ROM (0xFFF00000). If it is moved to soldered ROM with the pflash command it will not function properly. Thus it is not possible to move PPC5-Bug to soldered ROM and use it to pflash the VxWorks bootrom into socket flash.
Do not attempt to pflash VxWorks into the socketed ROM with PPC5-Bug. The pflash command will fail and you will destroy the PPC5-Bug image which resides in socketed ROM, resulting in an unuseable board. Use the pflash command only to program VxWorks into the soldered ROM as explained above.
This section describes miscellaneous information concerning this BSP and its use.
The delivered objects are: bootrom, vxWorks, vxWorks.sym, and vxWorks.st.
The make targets are listed as the names of object-format files.bootrom
bootrom_uncmp
vxWorks (with vxWorks.sym)
vxWorks.st
vxWorks.st_rom
The routines sysInWord/sysOutWord and sysInLong/sysOutLong are defined the same as the PCI version of these functions, respectively sysPciInWord/sysPciOutWord and sysPciInLong/sysPciOutLong. If any additional drivers are to be added to this BSP and are expecting non-byte swapping data access, a new set of routines can be added to sysALib.s.
LoPEC requires PC-100 (or PC-133) SDRAM DIMMs. Systems using the MPC107 with 66MHz memory bus frequency may use unbuffered DIMMs. That is, systems with the MPC750 processor may use unbuffered DIMMs. Systems with higher memory bus frequencies (MPC7410) must use registered DIMMs.
The diagram below shows socketed flash and DIP switch bank configuration: XU2 and XU1 contain PPC5-Bug.
____________________________________________________________________ | J32 J19 || || J28 J27 J23 | | || || || || || || -------- | | || || J30 J29 || || | ----- | | | | || || COM3 COM2 || || | | | | |2| || || || || | | | | ||| SCSI Low || || | | | | +----------+ |R| Density || 2.5" | ----- | | || |||||| || |O| Parallel 3.5" EIDE -------- | | |Processor|| |W| Port EIDE Compact Flash | | || |||||| || | | | | +----------+ |D| ------- | | |I| | J15 | | | |M| ------- | | |M| High +----\ | | |S| Density S1 |XU2 | | | | | Parallel :: +----+ | | Port :: | | :: | | :: +----\ | | 8-DIP |XU1 | | | switch +----+ | | COM1 er0 bank | | serial 10/100BaseT | |__----_______----___________________________________________________|
Tornado User's Guide: Getting Started, VxWorks Programmer's Guide: Configuration
MPC7400 User's Manual , MPC750 RISC Microprocessor User's Manual Motorola PowerPC Microprocessor Family: The Programming Environments, Motorola Computer Group Online Documentation, http://library.mcg.mot.com/mcg/boards , Intel 82559ER Fast Ethernet PCI Bus Controller with Integrated PHY, SGS-Thomson M48T37v 32KB RTC/NVRAM Data Sheet, Peripheral Component Interconnect (PCI) Local Bus Specification, Rev 2.1, PCI to PCI Bridge Architecture Specification 2.0, IEEE P1386.1 Draft 2.0 - PCI Mezzanine Card Specification (PMC),