ebony - IBM PPC440GP EVB
This manual entry provides board-specific information necessary to run VxWorks for the ebony (IBM PPC440GP) BSP. Before using a board with VxWorks, verify that the board runs in the factory configuration by using vendor-supplied ROMs and jumper settings and checking the RS-232 connection.
This BSP supports the PowerPC 440GP Rev 2.0 parts. Although it may work on Rev 1.0 or Rev 1.1, only Rev 2.0 operation has been validated.
The IBM 440GP Evaluation Board uses a single AMD Am29F040 ROM (total 512KB) as a boot device. You may create a bootrom or vxWorks standalone rom image (vxWorks.st_rom). Install the ROM as follows:
Boot parameters are preserved when the system is powered off in the NVRAM (Dallas Semiconductor DS1743) on the ebony board.
ROM Socket - U60 To load VxWorks, and for more information, follow the instructions in the Tornado User's Guide: Getting Started.
The following switch settings apply:
Part Setting Description U46, SW1 OFF = 1 Boot from Small ROM (U60) U46, SW2 ON = 0 FLASH on Board U46, SW3 ON = 0 FLASH at Top of Program Memory U46, SW4 OFF = 1 Use 440GP internal PCI arbiter
The following jumper settings apply:
The contents of the IIC bootstrap device set up the following clock parameters:
Part Setting Description J41 1-2 Select bootstrap device at IIC0 address 0xA8 (U29) J42 Open IIC Bootstrap controller enabled - Processor speed of 400MHz
- Processor Local Bus (PLB) speed of 133MHz
- DDR SDRAM speed of 266MHz
- On-chip Peripheral Bus (OPB) speed of 66MHz
- External Peripheral Bus (EBC) speed of 66MHz
The following features are supported in this release:
- One or two DDR SDRAM DIMMs, with SPD-based auto-initialization
and ECC support. Cas Latencies 2.0, 2.5, and 3.0 are supported.
DIMMs may optionally be registered and/or ECC. VxWorks has been
tested with Micron MT8VDDT1664AG-265A1 (128MB, DDR, 266MHZ,
CL2.5) and Micron MT8VDDT1672AG-265A1 (128MB, DDR, 266MHZ, CL2.5,
ECC), individually and together.
- 440GP 8KB on-chip SRAM
- 440GP static TLB setup for operation without MMU library
- System Timer (uses 440GP Decrementer) using external or internal
clock
- Both 440GP integrated 16550-style serial ports using external or
internal clock
- 440GP integrated dual Universal Interrupt Controllers (UIC)
- WDB and TSFS
- CrossWind debugger, including system-mode
- Windsh
- Browser & C-Spy
- Solaris development host
- dwarf-2 symbols for use with RISCWatch and SingleStep debuggers
- 440GP MAL/EMACs/ZMII (integrated Memory Access Layer, 10/100
Ethernet MAC, and Z media independent interface)
- Auxiliary Timer (uses 440GP FIT hardware timer)
- Watchdog Timer using 440GP WDT hardware timer
- Timestamp driver using Auxiliary Timer
- 440GP PCI-X controller and autoconfiguration for PCI conventional
devices
- NVRAM (Dallas Semiconductor DS1743)
- Real-time clock (Dallas Semiconductor DS1743) using ds1643rtc.c driver
- AMD 79C97x family of Ethernet controller (using ln97xEnd driver)
- Allied Telesyn AT-2450FTX adapter (AMD 79C972) has been tested.
- Allied Telesyn AT-2700TX adapter (AMD 79C972) has been tested.
- 2 Large (2MB) Flash devices (Am29F016D)
- TFFS flash filesystem using the 4MB large flash array
- 440GP MMUs (MMU_BASIC)
- 440GP IIC bus for SDRAM SPD autodetection at boot (only)
- 440GP Caches in disabled, writethrough and copyback modes
- WindView host tools
- Windows NT development host
- 440GP DMA
- 440GP General Purpose Timers (GPTs)
- 440GP IIC bus
- IrDA Port
This section documents the details of the device drivers and board hardware elements.
The chip drivers used by this bsp are:evbNs16550Sio.c - 16550 serial driver
ppc440Timer.c - timer driver for the PPC440 processor core
ibmEmacEnd.c - END style IBM EMAC Ethernet driver
malLib.c - IBM Memory Access Layer (MAL) driver
pciAutoConfigLib.c - PCI bus scan and resource allocation facility
pciConfigLib.c - PCI Configuration space access support for PCI drivers
uicIntr.c - Universal Interrupt Controller (UIC) driver
sysDcr.s - Generic DCR register access routinesThis bsp also provides the following chip drivers:
d1643RTC.c - RTC DS1643 real time clock driver
byteNvRam.c - byte-oriented generic NVRAM driver
ln97xEnd - END style AMD Am79C97X PCnet-PCI Ethernet driver
Immediately following a reset, the processor hardware initializes a temporary entry in the shadow TLB to map a 4KB block of memory at 0xfffff000 to the physical boot device address space at 0x1.fffff000. The processor commences execution at address 0xfffffffc. A branch instruction there jumps to the resetEntry function at address 0xfffff000.
resetEntry initializes a static MMU mapping of the PPC440GP processor's virtual address space. 16 memory regions are mapped with a TLB page size of 256MB each for a total size of 4GB. This map is in force until the MMU library is initialized:
The guarded attribute is not specified on one of the PCI Memory address regions (0xa0000000) to signal to the PCI-X controller that prefetching is allowed when this region is accessed.
Bootrom Static MMU Memory Map Program Addr Physical Addr Access Mode TLB Use 00000000 0.00000000 -I-G RWX 0 System RAM 10000000 0.10000000 -I-G RWX a System RAM 20000000 0.20000000 -I-G RWX b System RAM 30000000 0.30000000 -I-G RWX c System RAM 40000000 0.00000000 -I-G RW- 1 System RAM 50000000 0.10000000 -I-G RW- d System RAM 60000000 0.20000000 -I-G RW- e System RAM 70000000 0.30000000 -I-G RW- f System RAM 80000000 3.00000000 -I-G RWX 4 PCI Memory 90000000 3.10000000 -I-G RWX 5 PCI Memory a0000000 3.20000000 -I-- RWX 6 PCI Memory b0000000 3.30000000 -I-G RWX 7 PCI Memory c0000000 0.80000000 -I-G RWX 8 Internal SRAM d0000000 2.00000000 -I-G RW- 9 PCI e0000000 1.40000000 -I-G RW- 2 Peripherals f0000000 1.f0000000 -I-- RWX 3 Boot Space Following this initialization, resetEntry jumps to romInit to continue the boot procedure.
The vxWorks kernel supports 4KB page size dynamic TLB mapping and access mode control of the DDR SDRAM and SRAM devices. To accomplish this, configure INCLUDE_MMU_BASIC. During MMU library initialization, the kernel uses the sysStaticTlbDesc[] array to reinitialize the static TLB entry registers, with cache and access modes as identified by the array. The default configuration establishes this memory map:
If you have configured INCLUDE_TFFS, the Boot Space region will be set cache-inhibit instead (this is a requirement of the flash device driver).
vxWorks Static MMU Memory Map Program Addr TS Physical Addr Access Mode TLB Use 00000000 0 0.00000000 ---- RWX 0 System RAM 10000000 0 0.10000000 ---- RWX a System RAM 20000000 0 0.20000000 ---- RWX b System RAM 30000000 0 0.30000000 ---- RWX c System RAM 40000000 0 0.00000000 -I-- RW- 1 System RAM 50000000 0 0.10000000 -I-- RW- d System RAM 60000000 0 0.20000000 -I-- RW- e System RAM 70000000 0 0.30000000 -I-- RW- f System RAM 80000000 0/1 3.00000000 -I-G RW- 4 PCI Memory 90000000 0/1 3.10000000 W--- RW- 5 PCI Memory a0000000 0/1 3.20000000 -I-G RW- 6 PCI Memory b0000000 0/1 3.30000000 -I-G RW- 7 PCI Memory c0000000 0 0.80000000 ---- RWX 8 Internal SRAM d0000000 0/1 2.00000000 -I-G RW- 9 PCI e0000000 0/1 1.40000000 -I-G RW- 2 Peripherals f0000000 0/1 1.f0000000 W--- RWX 3 Boot Space In addition, the sysPhysMemDesc[] array is used to map arbitrary program addresses to physical address spaces, with a 4KB page size. This table describes the region of memory mapped via the 4KB page descriptors managed by the virtual memory library (vmBaseLib). Note that the sysPhysMemDesc[] array only supports 32-bit physical addresses, so fine-grained MMU support on Ebony is limited to the DDR SDRAM and Internal SRAM devices. The memory map for the vmBaseLib-managed area is as follows:
vxWorks Dynamic MMU Memory Map Program Addr Physical Addr Access Mode Size Use 00000000 0.00000000 ---- RWX SDRAM-Size System RAM c0000000 0.80000000 ---- RWX 8 KB Internal SRAM
The BSP's default cache mode may be used to globally change the attributes of the caching areas in the VxWorks Memory Map. The default cache mode may be changed using the USER_D_CACHE_MODE and USER_I_CACHE_MODE configuration parameters. USER_D_CACHE_MODE is used by sysLib.c to set cache attributes on individual memory regions described by the sysStaticTlbDesc[] and sysPhysMemDesc[] arrays.
Valid values are CACHE_DISABLED, CACHE_WRITETHROUGH, or CACHE_COPYBACK (the default). If you set USER_D_CACHE_MODE to CACHE_COPYBACK, the cache attributes for each vxWorks kernel region will appear exactly as in the vxWorks Static and Dynamic Memory Map tables above. If you set it to CACHE_WRITETHROUGH, regions in the tables above that do not already have the Inhibit bit set will have the Writethrough bit set. If you set it to CACHE_DISABLED, all regions will have the Writethrough bit clear, and the Inhibit bit set.
Due to design limitations in the VxWorks loader and vmBaseLib, if the cache is enabled for D-cache, it must be enabled for I-cache; and if it is disabled for D-cache, it must be disabled for I-cache. sysLib.c enforces these requirements.
The default configuration of the serial ports are 9600bps, 8 data bits, no parity, 1 stop bit.
The Enhanced Network Driver (END) used with the dual integrated EMAC Ethernet cores is "ibmEmacEnd". Note that the boot device name is now "emac", rather than "ibmEmac".
The EMAC devices share use of a single on-chip Memory Access Layer (MAL) device and multichannel Z Media Independent Interface (ZMII) controller.
Since MAL is a Processor Local Bus (PLB) master, its accesses to system memory are unknown to the processor's L1 cache because there is no hardware enforced cache coherency in the 440GP. The ibmEmacEnd driver maintains coherency for both buffer descriptors and buffers.
Polled mode operation which allows "system" level debug is supported.
The following features are not supported in the current driver:
- wake-on-LAN
The Ethernet hardware addresses used by the EMACs are configurable at run-time. The first three bytes of the address are always assumed to be 0x0004AC (IBM) and the last three bytes are configurable and stored in NVRAM at address 0xE8000500. To make the ethernet hardware address match the address printed on the decal attached to the Ebony board use the following example as a guide.
Ethernet hardware addresses on the Ebony board decal:
0004AC3E4B22 and 0004AC3E4B23
- boot VxWorks
- execute the following commands from the shell:sysLanIbmEmacEnetAddr0Set 0x00, 0x04, 0xAC, 0x3E, 0x4B, 0x22
sysLanIbmEmacEnetAddr1Set 0x00, 0x04, 0xAC, 0x3E, 0x4B, 0x23The Ebony board has two PHY devices. A RMII device (AMD Am79C875) and a SMII device (Intel LXT9762). Due to errata in the ZMII controller of the 440GP Rev 1.1 chip, only EMAC0 can be used with the RMII PHY. Both EMAC0 and EMAC1 can be used if the SMII PHY is being used. See 440GP Rev 1.1 errata ZMII_2 for more details.
The chart below is a summary of how to change the ebony board jumpers to select RMII mode or SMII mode. The ebony board is shipped in RMII mode.
Jumper RMII mode SMII mode J33 2-3 1-2 J34 2-3 1-2 J78 1-2 2-3 J79 2-7 1-8 J79 4-5 3-6 J80 2-7 1-8 J80 4-5 3-6 If desired, an AMD 79C97x PCI Ethernet card can be plugged into the Ebony board. This controller uses the ln97xEnd driver provided with Tornado 2.0.
If PCI adapter cards are plugged into the slots of the Ebony board, be sure to set the U80 switches 2 and 3 so the C9531 PCIX I/O System Clock Generator supplies the proper PCI clock. For instance, if you place a 33MHz PCI card into one of the slots, set U80 switches 2 and 3 to the ON position.
PCI Bus Speed U80 SW3 U80 SW2 33MHz ON ON 66MHz ON OFF 100MHz OFF ON 133MHz OFF OFF
The following Tornado bootrom file types are known to work in this release:
- bootrom
- vxWorks_romCompressThe uncompressed images generated are too large to fit in the 512KB ROM.
a) Connect a terminal or terminal emulator to the board (the 9 pin
connector closest to the printed circuit board). Emulator
parameters should be set to 9600bps, 8 data bits, no parity, 1 stop
bit.b) Build a hex file
- make bootrom.hex
c) program it into an AMD 29F040 flash part and power up the board,
OR if you have a JTAG RISCWatch processor probe, see below.d) After the boot banner, you may get an error because the default boot
line in config.h is not 100% correct for your environment. Type in
new configuration parameters using the bootrom menu.
An IBM RISCWatch based command file (vx_rw_flash.cmd) is provided that will program a bootrom image (bootrom.hex) into the AMD Am29F040 flash part on the Ebony board. A RISCWatch JTAG processor probe and RISCWatch software version 4.7 or newer is required to use this utility.
Note: The vx_rw_flash.cmd utility may need modification if you use a different DDR SDRAM DIMM than was shipped with the Ebony board (see notes inside vx_rw_flash.cmd).
To use this utility,
a) make bootrom.bin (or other bootable image)
b) Start IBM RISCWatch
c) Make sure that the RISCWatch search path is set up to find files in
the Ebony BSP directory. One way to do this is to use the
"srchpath" command.d) Execute the following command to start the flash programming
process. This example will place the bootrom.hex file into
the flash.exec vx_rw_flash.cmd{"bootrom.hex"}
An IBM RISCWatch JTAG debugger may be used in place of the bootrom.
a) Change U46, SW3 to OFF = 1. This will map the 512KB off-chip SRAM at
address 0xfff80000. Power on the board.b) attach the RiscWatch, and connect to it with its GUI.
c) create a binary image file via step b) of the "Creating a bootrom"
section, above. If you created a hex file instead, you can convert
it to a binary image. This example assumes you created a
"bootrom.hex" file:objcopyppc -I srec bootrom.hex -O binary bootrom.bin
d) extract the final 4KB of the RAM image using this command sequence
(this works on Solaris; on Windows you can find dd.exe from
various sources. Search the WWW for "win32 gnu dd", or consider
the commerical product MKS Toolkit):dd if=bootrom.bin bs=4096 skip=127 count=1 of=last4k.bin
e) issue the following commands to RiscWatch:
stop
write EBC0_B0CR 0xfff18000
write EBC0_B0AP 0x9b015480
reset core
load bin last4k.bin 0xfffff000
asmstep 256
load bin bootrom.bin 0xfff80000
reset sysThis will stop the 440GP CPU core, set the Boot Space parameters to
access the SRAM device, reset the core (setting up a temporary TLB
mapping to the upper 4k of memory), load the upper 4k of memory, run
the CPU to set up more TLB access to the entire boot space, load the
full image into the top 512KB of memory, and reset the system to
begin normal execution out of the boot space.f) continue with step d) of the "Creating a bootrom" section above.
To use RISCWatch with BSP code or VxWorks application code, the following compiler options are necessary to get the proper debug information into the executable.-gdwarf-2 -O0
As an alternative, the Crosswind debugger may be used to debug the image in system mode via the second serial port.
Crosswind may be used to debug the ebony's execution via the standard network connections. Use the Tornado launcher to start a target server and crosswind.
Either the project facility or the command line, using make, may be used to build ebony projects.
Please see the "Terminology" sections of the Tornado User's Guide (Windows Version) for more information on bootable applications and downloadable applications.
There are errata in the 440GP Rev 1.0 chip that affect the operation of this Board Support Package. You should familiarize yourself with them. A current 440GP errata list is available from the PowerPC Technical support group (ppcsupp@us.ibm.com).
Cache cannot be supported on these devices.
If you are using a 440GP Rev 1.0 be sure to define PPC440GP_REVA in config.h.
There are errata in the 440GP Rev 1.1 chip that affect the operation of this Board Support Package. You should familiarize yourself with them. A current 440GP errata list is available from the PowerPC Technical support group (ppcsupp@us.ibm.com).
Workarounds for MAL Burst mode errata and support for Forward Clock B divisor differences are present in this BSP, but unsupported.
If you are using a 440GP Rev 1.1 be sure to define PPC440GP_REVB in config.h.
There are errata in the 440GP Rev 2.0 chip that affect the operation of this Board Support Package. You should familiarize yourself with them. A current 440GP errata list is available from the PowerPC Technical support group (ppcsupp@us.ibm.com).
This board support package is configured for Rev 2.0.
If you are using a 440GP Rev 2.0 be sure to define PPC440GP_REVC in config.h.
Due to MAL errata, bootroms built for 440GP Revision 2.0 will not function in a Revision 1.1 board.
The static TLB entry memory map defined in resetEntry (romInit.s) and sysStaticTlbDesc[] (sysLib.c) supports maximum 1GB of DDR SDRAM. This may be increased to 2GB (which is the maximum supported by DDR SDRAM controller) if the static TLB initialization is modified to map them and the limitation is removed from sysPhysMemTop( ) and sdramAutoConfig( ).
The Auxiliary Clock driver (in ppc440Timer.c) is implemented using interrupts provided by FIT interrupt divider taps. This means there are four rates available, in multiples of 16 apart. The lowest rate can be a number less than 10 and, due to integer rounding error, may refer to an actual rate corresponding to nearly a full integer larger. The Validation Test Suite expects the Auxiliary Clock to be able to reproduce arbitrary rates with an accuracy of 10%. It will log these results as errors.
SPR #79873. The memory mapping and TLB attributes set in romInit.s configure the boot instruction and SDRAM spaces as cache-inhibited. This results in slow performance during the boot process. Once the kernel is loaded and the MMU library is initialized, performance improves.
SPR #79925. Rom-resident images may be built, but are not functional and are not supported at this time.
Tornado User's Guide: Getting Started, VxWorks Programmer's Guide: Configuration, VxWorks Programmer's Guide: Architecture Appendix
Please refer to the following documents for further information on the Ebony board.
PowerPC 440 Reference Board Manual