VxWorks BSP Reference : cpv3060
cpv3060 - Motorola CPV3060
This note provides board-specific information necessary to run VxWorks. Before running VxWorks, verify that the board runs in the factory configuration (i.e. EPPC1-Bug (tm) mode). The cpv3060 BSP produces a VxWorks image running on the PowerPC MPC860T processor.
The PowerPlus architecture boards have two sets of FLASH memory. A set of AMD Am29F040 FLASH ROMs is socketed and contains Motorola's EPPC1-Bug (tm) and a set of soldered FLASH parts. The VxWorks boot kernel resides in the soldered FLASH. Follow the instructions in the section, "ROM considerations", below to load and write the boot kernel image to the soldered FLASH.These boards have non-volatile RAM. Thus, boot parameters are preserved whenever the system is powered off.
To load VxWorks, and for more information, follow the instructions in the "Getting Started" chapter of the VxWorks Programmer's Guide.
The following jumpers are relevant to VxWorks configuration:
Motorola CPV3060 Jumper Function ----------------------------------------------------- W1 On-board Battery 1-2 On-board battery connect (required for operation) 2-3 On-board battery disconnected W2 Select Boot Device 1-2 ROM - Socket 2-3 ROM - Main Flash Notes: When W2 is set for 1-2 Socketed ROM base address = 0xFE00_0000 Main Flash ROM base address = 0xFC00_0000 When W2 is set for 2-3 Main Flash ROM base address = 0xFE00_0000 Socketed ROM base address = 0xFC00_0000 W3 Boot ROM 1-2 Enable writing to Boot ROM 2-3 Boot ROM write protect
This section describes the supported and unsupported features of the CPV boards.
The supported features of the CPV board are:
MPC860T processors
Board Initialization
MMU support
Cache support
Timer driver
Serial driver
Fast Ethernet END driver
PCI Host Bridge (QSPAN)
I2C Bus
Optional serial port (SCC2)
Optional Synchronous Burst RAM
16MB, 32MB, 64MB or 128MB onboard memory
50, 100 MHZ CPU speeds
The unsupported features of the CPV board are:
Hot Swap
64-bit PMC cards
Watchdog Timers
TSA/TDM Channels
SPI
I2C write capability
This section documents the details of the device drivers and hardware elements for the CPV board.
The chip drivers included are:
qspanPci.c - QSpan PCI to Motorola Bridge motFecEnd.c - Motorola Fast Ethernet Controller END driver ppcDecTimer.c - PowerPC Timer library ppc860Sio.c - Serial Communications library for SMC1 port ppc860SioScc.c - Serial Communications library for SCC2 port sysSerial.c - Serial port configuration file ppc860Intr.c - Interrupt Controller library i2cMcp.c - I2C micro-chip patch cpvI2c.c - I2C bus access byteNvRam.c - NVRAM access routines
The board support package for the CPV3060 handles automatic detection and configuration of compact PCI devices. In particular, it performs the following:
- 1)
- Probes the host PCI bridge for all devices on the host PCI bus (bus zero). Note that among the devices on bus zero might be PCI-PCI bridges. These bridges are probed as well and recursive probing occurs until all devices and bridges are found.
- 2)
- Memory is assigned to each device and sub-bridge found. For devices, each Base Address Register (BAR) is queried. Memory or I/O space (or both) is allocated for each BAR which has been implemented.
- 3)
- Complete initialization of the devices is performed, including cache Line size, command register, latency timer, interrupt line and base address registers (0 through 5). PCI-PCI bridges are initialized with the correct primary bus, secondary bus and subordinate bus designation. In short, the entire bridge/device "tree" rooted at the host pci bridge is completely configured and ready for driver access.
A new feature to the PCI autoconfiguration is "roll call". If you expect to find a certain number of specific devices identified by device/vendor ID during PCI autoconfiguration you can enter the information into a roll call list. For example assume that you know that the autoconfiguration process should find 4 different devices with device/vendor ID of 0x00461011 (this would be the Dec2155x device). You want PCI autoconfiguration to "wait" until it finds at least this many but you don't want it to wait more than 20 seconds. If 20 seconds have elapsed and 4 different Dec2155x chips have not appeared in the bus enumeration process, you would like the PCI autoconfiguration process to proceed anyway.
You would construct the "roll call" list in "config.h" as shown below:
#define ROLL_CALL_MAX_DURATION 20
#define PCI_ROLL_CALL_LIST_ENTRIES \ { 4, 0x00461011 },
The parameter ROLL_CALL_MAX_DURATION specifies that no more than 20 seconds should elapse before proceeding on with the autoconfiguration, even though less than 4 Dec2155x devices have been found.
You can see the entry { 4, 0x00461011 } which says that you expect to find at least 4 devices whose device/vendor ID is 0x00461011. Note that "cpv3060.h" contains defines for some device/vendor IDs, such a define could be used here instead of a hard-coded device/vendor ID.
Also note that this list can be extended so more than one device/ vendor ID is identified with possibly a different count.
If the list is empty (except for the termination entry) then there is no roll call waiting performed, regardless of the setting of ROLL_CALL_MAX_DURATION.
The roll call feature can be useful for devices which are slow to appear on the cPCI bus. For example, CPV3060 CPU boards (which contain the Dec2155x nontransparent PCI bridge) will not be visible to a cPCI master which is enumerating the bus until the CPV3060 clears the "primary access lock-out" bit in the Dec2155x chip control 0 register. If the master's bus enumeration occurs before the CPV3060 software unlocks the Dec2155x, then the master will not know the CPV3060 is present and will not configure it. The roll call feature allows for bus enumeration polling until the specified devices actually appear. Note that roll call may not always be required for the example just presented. Some system configurations and timings may work without using the roll call feature.
This BSP contains support for the Dec2155x non-transparent PCI-to-PCI bridge. This device provides read/write access to and from the Compact PCI bus (cPCI).The following support is provided:
Up to 4 user configurable downstream cPCI to local PCI windows. Up to 2 user configurable upstream local PCI to cPCI windows. Support for in-bound "doorbell" interrupts. Support for cPCI backpanel interrupts. cPCI to local CPU address translation. Local CPU to cPCI address translation. Build-time validation of Dec2155x configuration parameters.
The PReP standard does not support 64-bit PCI addressing. Therefore, this BSP does not provide support for 64-bit addressing through the Dec2155x.There is a limitation when the cPCI to local PCI or cPCI to local CPU address translation routines are presented with a cPCI address which maps into a downstream window on the local board. The translation will succeed and return an address, but when that address is accessed, the Dec2155x will attempt to access one of its own downstream windows. The transfer will fail because PCI devices cannot access themselves on the cPCI bus. Depending on how error detection is configured, the result will be invalid data or a PCI Master Abort.
Interrupt vectors are provided for the interrupts associated with Dec2155x Hot Swap Power State transitions, Intelligent I/O (I2O), and the Upstream Memory 2 Base Address Register but no other support for these features is provided.
During system startup, the Dec2155x must be configured and unlocked before the host enumerates the cPCI bus. To meet this timing requirement, the Dec2155x is configured by the vxWorks boot ROM image. If changes to the Dec2155x configuration are made, new boot ROMs are required in addition to a new kernel. For proper operation, the Dec2155x configuration in the Boot ROMs must match the configuration used by the kernel.
The Dec2155x places certain limitations on window sizes and translation values. This BSP adheres to those limitations and provides build-time parameter checking to help avoid misconfigurations. Modifications to the default Dec2155x configuration provided in this BSP must be made with care to avoid invalid configurations. Information on the default Dec2155x configuration provided by this BSP is presented in the next section and modification guidelines appear later in this file.
The default Dec2155x configuration supports a host processor (MCP750) and up to 7 CPV3060s. The following interoperability is supported:
Host access to CPV3060 CSR and the low 4MB of CPV3060 DRAM. CPV3060 access to the low 4MB of host DRAM. CPV3060 access to peer CPV3060 CSR and low 4MB of peer CPV3060 DRAM.
The BSP provides these features using the following Dec2155x configuration:
Primary CSR and Downstream Memory 0 BAR: Size: 4MB Direction: In-Bound (cPCI to CPV3060) cPCI Adrs: Dynamic (assigned by host) Local PCI Adrs: PCI2DRAM_BASE_ADRS (0x80000000 by convention) Local PCI Adrs: Dynamic (assigned by CPV3060) Local CPU Adrs: Dynamic (based on local PCI adrs) Use: R/W access to host DRAM The remaining Dec2155x Base Address Registers are not used by the BSP and are available for use by the application.
Upstream Memory 1 BAR: Size: 32MB Direction: Out-Bound (CPV3060 to cPCI) cPCI Adrs: Base cPCI address of the host's dynamic PCI configuration area (0x02000000 for the default MCP750 BSP) Local PCI Adrs: Dynamic (assigned by CPV3060) Local CPU Adrs: Dynamic (based on local PCI adrs) Use: R/W access to cPCI devices
Due to the dynamic nature of PCI address allocation, the locations of the upstream Dec2155x windows move as devices are added to the CPV3060 PCI bus. Since these windows map the cPCI space into the local CPV3060 PCI and CPU address spaces, their positions determine where the cPCI resources appear when viewed by the CPV3060 CPU and any CPV3060 resident PCI devices. Likewise, the downstream windows move as cPCI devices are added and removed. The downstream windows are used to map the on-board PCI and DRAM resources into the cPCI address space for access by the host and other cPCI devices.To assist with address translation, two translation routines are provided by this BSP:
NOTE: The translations performed by sysLocalToBusAdrs( ) and sysBusToLocalAdrs( ) are not symmetrical if one of the endpoints is the Compact PCI bus. sysLocalToBusAdrs( ) translates by locating a downstream window which makes the local CPU address visible in the cPCI address space. sysBusToLocalAdrs( ) performs a similar operation by locating an upstream window which makes the cPCI address visible in the local CPU address space. Since the two sets of windows map different areas of the local address space, the translation is not reversible.
sysLocalToBusAdrs( ) Translates a local CPU address to an equivalent cPCI or local PCI memory or I/O address. sysBusToLocalAdrs( ) Translates a cPCI or local PCI memory or I/O space address to a local CPU equivalent address.
Due to dynamic PCI address allocation, the PCI address assigned to the Dec2155x CSR area cannot be known until runtime. To determine the assigned address, it is necessary to read the Secondary CSR memory BAR (or the Secondary CSR I/O BAR if I/O space is to be used).The following code fragment derives the CPU address of the Scratchpad 0 register using its PCI memory space address:
UINT32 bar; /* get the contents of the secondary CSR memory BAR (see note below) */ if (pciConfigInLong (0, DEC2155X_PCI_DEV_NUMBER, 0, DEC2155X_CFG_SEC_CSR_MEM_BAR, &bar) != OK) { return (ERROR); } /* calculate the local PCI address of the scratchpad 0 register */ bar += DEC2155X_CSR_SCRATCHPAD0; /* convert the result to the CPU equivalent address */ if (sysBusToLocalAdrs (PCI_LOCAL_MEMORY_SPACE, (char *)bar, (char **)&bar) != OK) { return (ERROR); } return (bar);NOTE: Using the constant DEC2155X_PCI_DEV_NUMBER ensures that the on-board Dec2155x is read. If a search of the local PCI bus had been performed using the Dec2155x device ID, the returned Bus, Device and Function numbers may have corresponded to a Dec2155x part found on an installed PMC card.Once the local CPU address is known, the cPCI address can be derived by adding the following code fragment before returning the result:
if (sysLocalToBusAdrs (PCI_BACKPANEL_MEMORY_SPACE, (char *)bar, (char **)&bar) != OK) return (ERROR); else return (bar);
At start-up, all Dec2155x interrupt sources are masked and cleared. Before unmasking an interrupt, an application ISR service routine must be attached to the appropriate Dec2155x interrupt vector using intConnect( ). Multiple ISR service routines can be connected to each vector if required by the application. Once the handler is attached, the interrupt can be enabled and disabled by calling sysDec2155xIntEnable( ) or sysDec2155xIntDisable( ) as required. Interrupt vector definitions for the Dec2155x internal interrupt sources are defined in cpv3060.h.Unique interrupt vectors are provided for each of the 16 bits in the Dec2155x Secondary IRQ register. Bit 0 (LSB) corresponds to DEC2155X_DOORBELL0_INT_VEC with the remaining bits mapped in sequence. These doorbell interrupts can be used for host-to-CPV3060 or CPV3060-to-CPV3060 event notification. The Dec2155x interrupt handler clears these interrupts which simplifies the application ISR.
Individual interrupt vectors are also provided for Dec2155x Hot Swap Power State and I2O in-bound list events. The Dec2155x interrupt handler also clears these interrupts.
The 64 Upstream Memory 2 BAR Page Crossing interrupts are all presented on a single interrupt vector and the application ISR is responsible for clearing the bits serviced. Calls to sysDec2155xIntEnable( ) and sysDec2155xIntDisable( ) enable or disable all 64 interrupts.
The Dec2155x interrupt handler provides a default service routine for all unclaimed interrupt vectors, including the Upstream Memory 2 BAR Page Crossing interrupt. The default routine reports the event and clears the interrupt source.
The Dec2155x can generate cPCI backpanel interrupts using any of the bits in the Primary IRQ register if they have been un-masked by the host. The following code fragment generates a compact PCI backpanel interrupt by setting bit 15 (MSB) of the Primary IRQ register:if (sysBusIntGen (DEC2155X_DOORBELL15_INT_LVL,
DEC2155X_DOORBELL15_INT_VEC) != OK)
return (ERROR);Note that the cPCI bus does not provide an interrupt vector to the host. The vector number passed to sysBusIntGen( ) simply identifies which bit in the register to set. It is the host's responsibility to locate the interrupt source and clear the interrupt.
In-bound cPCI backpanel interrupts are routed directed to the CPV3060 CPU via the SIU. They can be enabled, disabled and handled by calling sysIntEnable( ), sysIntDisable( ) and intConnect( ) with the vector number of the desired backpanel interrupt line.
NOTE: Great care must be exercised when cPCI backpanel interrupts are being generated and received simultaneously. If the packpanel interrupt line driven by the CPV3060 is also enabled for receiving interrupts, the CPV3060 will be interrupted by its own backpanel interrupt. This scenario causes complications because the backpanel interrupts are configured as level sensitive and difficulties are encountered in determining the party responsible for clearing the interrupt source. In general, backpanel interrupt generation is useful for signaling an event to the host, but in-bound packpanel interrupts have limited usefulness.
Altering the Dec2155x configuration requires the careful consideration of several items:
Dec2155x window sizes and alignment. Dec2155x translation values. The size and alignment of the host's dynamic PCI configuration area. The size and alignment of the CPV3060's dynamic PCI configuration area.
The Dec2155x window parameters are controlled by #defines in config.h. There are three defines associated with each window:
..._SIZE determines the size of the window in bytes and must be an integral power of two. The minimum size for a PCI I/O space window is 64 bytes. The minimum size for a PCI memory space window is 4KB. To disable a window, set the size to 0. Note that the Dec2155x will not allow the Primary CSR and Downstream Memory 0 BAR to 0 to be disabled. If the size of this window is set to zero, the Dec2155x will default to a 4KB window. NOTE
If a window value is not a power of 2, or is below the minimum size, sysLib.c will not compile.
..._TYPE determines the type of the window and any placement restrictions. For proper operation, the window must be configured for placement anywhere in the 32-bit PCI address space. The default window sizes can be reduced without altering the sizes of the dynamic PCI configuration area. However, if the required values are significantly reduced from the default values, reducing the size of the dynamic PCI configuration area reduces the size of the MMU page tables at the ratio of 128:1 (a 128KB reduction saves 1KB of MMU table space).
..._TRANS determines the base address of the window on the target PCI bus. It is important to remember that this is a local PCI address (downstream window) or a cPCI address (upstream window). The translation value chosen must be an even multiple if the window size. NOTE
If the translation value is not a multiple of the window size, sysLib.c will not build. The size of the PCI memory space used for dynamic PCI configuration is controlled by PCI_MEM_SIZE in config.h and the area's base address is controlled by CPU_PCI_MEM_ADRS in cpv3060.h. By default, the PCI master MCP750 BSP allocates a 32MB area aligned to a 32MB boundary for dynamic PCI configuration. To access peer CPV3060 DRAM areas, an upstream window must be opened which matches the size of the host's dynamic PCI configuration area. For translation to work correctly, the host's dynamic PCI configuration area must be aligned to a multiple of the area's size and the corresponding Dec2155x upstream translation register must contain the area's base cPCI address (not CPU address). Since this BSP supports peer-to-peer access between CPV3060 DRAM areas, the default dynamic PCI configuration area for the CPV3060 is 64MB aligned to a 32MB boundary which satisfies these requirements.
In addition to the peer access window, sufficient space must also be available for mapping the host DRAM upstream window and any space required by CPV3060-resident PCI devices. A margin must also be allowed for areas that are unusable due to window alignment requirements.
If the application does not require peer-to-peer CPV3060 DRAM access, the large 32MB window used to contain the host's dynamic PCI configuration area can be eliminated with a corresponding decrease in the required CPV3060 dynamic PCI configuration area. If peer-to-peer doorbell interrupts are still required, the doorbell interrupt registers of peer CPV3060s may be accessed through an I/O window which has much smaller CPU address space requirements. This would require re-configuring the default BSP to access host DRAM through Upstream Memory 1 BAR and using the Upstream I/O or Memory 0 BAR to access the peer CPV3060 doorbell interrupt registers.
The CPV3060 supports shared memory backplane communication. The Wind River documentation provides a great deal of information regarding shared memory concepts. The section below provides tutorial style information regarding the setup of a shared memory system involving the MCP750 (PCI bus master) and CPV3060(s).
Setting up a working shared memory system involves proper setting of certain "config.h" parameters and proper setting of boot parameters via the "c" command from the boot prompt. There are three components involved in shared memory communication which must be configured properly to create a working system:
The following restrictions apply to shared memory configurations.
- Anchor:
- This is an area of memory which must be accessible to all nodes participating in shared memory backplane communication. The anchor points to the actual shared memory buffer pool which must be located in the same memory space as the anchor itself. The associated "config.h" parameter is SM_ANCHOR_ADRS. In certain configurations, nonzero nodes will "poll" for the location of the anchor. "config.h" defines which comes into play for polling are SM_OFF_BOARD and SYS_SM_SYSTEM_MEM_POLL.
- Master node:
- This node is always designated as node zero. It is the node which sets up the anchor and shared memory pool. Once the anchor and shared memory pool is set up, the master node acts as a peer with the other nodes. The node number (0 in this case) is one of the boot parameters which can be set up with the "c" command from the bootline prompt.
- Sequential addressing:
- This is is governed by a "config.h" parameter, INCLUDE_SM_SEQ_ADDR and is used when sequential IP addresses are assigned to the participating nodes. Node zero is assigned the lowest IP address, followed by nodes 1, 2 etc. which are assigned the subsequent and sequential IP addresses. The advantage of sequential addressing is that fewer boot parameters must be specified to configure the system.
Note: Another piece of shared memory terminology is "host node". The "host node" is the node which configures the compact PCI bus during startup initialization. In a system consisting of an MCP750 and one or more CPV3060s, the "host node" is the MCP750. Don't confuse "host node" with "master node". "Master node" is simply a synonym for "node 0". The "host node" may or may not be the "master node". Note also that the "host node" need not necessarily be a VxWorks node.
- 1)
- Node zero must not boot over the shared memory interface. Only nonzero nodes are allowed to boot over the shared memory "sm" interface.
- 2)
- The location of the anchor must be statically determinable by the master node (node 0). That is, the location of the anchor must either be a build-time static parameter or it must be able to be communicated to the master node via the "sm=xxxxxxxx" boot configuration parameter. The nonzero nodes need not know the location of the anchor at build or boot time but can be configured to poll for the anchor dynamically.
Below are the crucial "config.h" parameters involved in shared memory:
Consider a system consisting of an MCP750 (host node) and two CPV3060s. The following six configurations are the only ones possible:
- SM_OFF_BOARD (TRUE or FALSE):
- The parameter has a configurable value of either TRUE or FALSE and directly determines the value of SM_ANCHOR_ADRS (the anchor address).
If SM_OFF_BOARD is defined as FALSE, then the anchor is on-board and SM_ANCHOR_ADRS is defined to be LOCAL_MEM_LOCAL_ADRS + SM_ANCHOR_OFFSET. LOCAL_MEM_LOCAL_ADRS is defined as 0x0 in "config.h" and SM_ANCHOR_OFFSET is defined as 0x4100 in "config.h".
If defined as TRUE, then SM_ANCHOR_ADRS is defined as a function call: sysSmAnchorAdrs( ) (defined in "sysLib.c"). This function will dynamically poll, at system startup, various locations (explained below) for the exact location of the shared memory anchor.
Note that if "sm=xxxxxxxx" is used as a boot parameter, then SM_OFF_BOARD has no effect. The value of "xxxxxxxx" will be used as the anchor location regardless of the setting of SM_OFF_BOARD. If simply "sm" is used as a boot parameter, then SM_OFF_BOARD is queried at initialization time to determine if polling is required or not.
- SYS_SM_SYSTEM_MEM_POLL (#define or #undef):
- This define only has an effect if anchor polling is called for (because SM_OFF_BOARD is defined as TRUE and "sm" is used with no "=xxxxxxxx"). In this case, simply defining SYS_SM_SYSTEM_MEM_POLL will cause the node to poll for the anchor at compact PCI bus address PCI2DRAM_BASE_ADRS + SM_ANCHOR_OFFSET (0x80004100). "System memory" (which is the host node's DRAM) will be included as one of the locations where the anchor might reside. Note that other locations my be polled as well (explained later).
Not defining SYS_SM_SYSTEM_MEM_POLL will prevent the polling of system memory for the anchor.
- SYS_SM_ANCHOR_POLL_LIST (#define or #undef):
- This define has an effect only if polling is called for (see SM_OFF_BOARD explained above). When defined, SYS_SM_ANCHOR_POLL_LIST allows a list of devices, identified by device/vendor ID and subsystem ID/subsystem vendor ID to be specified as candidates for the anchor location. Devices which appear directly on the compact PCI bus are found and if they appear on the list defined by SYS_SM_ANCHOR_POLL_LIST, they are checked to see if they house the shared memory anchor. The memory defined by the first memory BAR is queried at offset SM_ANCHOR_OFFSET (0x4100 by default, defined in "configAll.h"). If SYS_SM_ANCHOR_POLL_LIST is not defined, ALL devices on the compact PCI bus will be considered candidates for the anchor location and will be polled. If SYS_SM_ANCHOR_POLL_LIST defined but empty, NO devices on the compact PCI bus will be considered candidates for the anchor location. In that case, the only location polled would be system memory if SYS_SM_SYSTEM_MEM_POLL (see above) was defined.
- INCLUDE_SM_SEQ_ADDR (#define or #undef)
- If "undef'ed", sequential addressing is disabled. This symbol is defined by default.
Below is a description of how each of the above systems would be configured. Crucial "config.h" and boot parameter settings for an example system are given. In each example, SYS_SM_ANCHOR_POLL_LIST was defined to contain information identifying the Dec2155x bridge chip (present on the CPV3060). See "config.h" for the example of how this was done.
Master node on... Anchor on... Sequential Addressing? 1. MCP750 MCP750 NO 2. MCP750 MCP750 YES 3. CPV3060 MCP750 NO 4. CPV3060 MCP750 YES 5. CPV3060 CPV3060 NO 6. CPV3060 CPV3060 YES
- 1)
- MCP750 master, MCP750 anchor, no sequential addressing:
MCP750: #define SM_OFF_BOARD FALSE #undef SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : dc host name : sunray processor number : 0 inet on ethernet (e) : 124.170.16.112 inet on backplane (b): 124.200.200.1:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : gamma CPV3060-1: #define SM_OFF_BOARD TRUE #define SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : sm host name : sunray processor number : 1 inet on ethernet (e) : 124.170.16.109 inet on backplane (b): 124.200.200.2 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.1 target name (tn) : alpha CPV3060-2: (same "config.h" setup as CPV3060-1 above) boot device : sm host name : sunray processor number : 2 inet on ethernet (e) : 124.170.16.110 inet on backplane (b): 124.200.200.3 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.1 target name (tn) : beta
- 2)
- MCP750 master, MCP750 anchor, sequential addressing:
MCP750: #define SM_OFF_BOARD FALSE #define SYS_CPCI_BUS_NUMBER 1 #undef SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : dc host name : sunray processor number : 0 inet on ethernet (e) : 124.170.16.112:ffffff00 inet on backplane (b): 124.200.200.1:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : gamma CPV3060-1: #define SM_OFF_BOARD TRUE #define SYS_CPCI_BUS_NUMBER 1 #define SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : sm host name : sunray processor number : 1 inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : target name (tn) : alpha CPV3060-2: (same "config.h" setup as CPV3060-1 above) boot device : sm host name : sunray processor number : 2 inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : target name (tn) : beta
- 3)
- CPV3060 master, MCP750 anchor, no sequential addressing:
MCP750: #define SM_OFF_BOARD TRUE #undef SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : sm host name : sunray processor number : 1 inet on ethernet (e) : 124.170.16.112 inet on backplane (b): 124.200.200.1 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.2 target name (tn) : gamma CPV3060-1: #define SM_OFF_BOARD FALSE #define SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : motfec processor number : 0 host name : sunray inet on ethernet (e) : 124.170.16.109 inet on backplane (b): 124.200.200.2:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : alpha CPV3060-2: #define SM_OFF_BOARD TRUE #define SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : sm processor number : 2 host name : sunray inet on ethernet (e) : 124.170.16.110 inet on backplane (b): 124.200.200.3 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.2 target name (tn) : beta
- 4)
- CPV3060 master, MCP750 anchor, sequential addressing:
MCP750: #define SM_OFF_BOARD TRUE #undef SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : sm processor number : 1 host name : sunray inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : target name (tn) : gamma CPV3060-1: #define SM_OFF_BOARD FALSE #define SYS_CPCI_BUS_NUMBER 1 #define SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : motfec processor number : 0 host name : sunray inet on ethernet (e) : 124.170.16.109:ffffff00 inet on backplane (b): 124.200.200.1:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : alpha CPV3060-2: #define SM_OFF_BOARD TRUE #define SYS_CPCI_BUS_NUMBER 1 #define SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : sm processor number : 2 host name : sunray inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : target name (tn) : beta
- 5)
- CPV3060 master, CPV3060 anchor, no sequential addressing:
MCP750: #define SM_OFF_BOARD TRUE #undef SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : sm processor number : 1 host name : sunray inet on ethernet (e) : 124.170.16.112 inet on backplane (b): 124.200.200.1 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.2 user (u) : ball ftp password (pw) (blank = use rsh): flags (f) : 0x0 target name (tn) : gamma CPV3060-1: #define SM_OFF_BOARD FALSE #undef SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : motfec processor number : 0 host name : sunray inet on ethernet (e) : 124.170.16.109 inet on backplane (b): 124.200.200.2:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : alpha CPV3060-2: #define SM_OFF_BOARD TRUE #undef SYS_SM_SYSTEM_MEM_POLL #undef INCLUDE_SM_SEQ_ADDR boot device : sm processor number : 2 host name : sunray inet on ethernet (e) : 124.170.16.110 inet on backplane (b): 124.200.200.3 host inet (h) : 124.170.16.143 gateway inet (g) : 124.200.200.2 target name (tn) : beta
- 6)
- CPV3060 master, CPV3060 anchor, sequential addressing:
MCP750: #define SM_OFF_BOARD TRUE #undef SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : sm processor number : 1 host name : sunray inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : target name (tn) : gamma CPV3060-1: #define SM_OFF_BOARD FALSE #undef SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : motfec processor number : 0 host name : sunray inet on ethernet (e) : 124.170.16.109:ffffff00 inet on backplane (b): 124.200.200.1:ffffff00 host inet (h) : 124.170.16.143 gateway inet (g) : 124.170.16.233 target name (tn) : alpha CPV3060-2: #define SM_OFF_BOARD TRUE #undef SYS_SM_SYSTEM_MEM_POLL /* #undef INCLUDE_SM_SEQ_ADDR */ boot device : sm processor number : 2 host name : sunray inet on ethernet (e) : inet on backplane (b): host inet (h) : 124.170.16.143 gateway inet (g) : flags (f) : 0x0 target name (tn) : beta
The current BSP only supports the Motorola FEC END driver.
On-board RAM for these boards always appears at address 0x0 locally Dynamic memory sizing is supported. By default, LOCAL_MEM_AUTOSIZE is defined so that the memory will be auto-sized at hardware initialization time. When auto-sizing is not selected, LOCAL_MEM_SIZE should be set to the size of DRAM memory available on the board so as to ensure full memory availability and proper VME addressing. The default fixed RAM size is set to 16 MB (see LOCAL_MEM_SIZE in config.h).The base addresses for the CPV memory setup are programmed in romInit.s, using the BR and OR registers.
Memory Map from CPU point of view Start Size Access to ------------------------------------------------------------------ 0x0 16MB (min) DRAM 0x0C000000 128KB (min) optional Burst RAM 0x80000000 64KB (min) PCI ISA I/O space 0x80010000 511MB (max) PCI I/O space 0xC0000000 64MB (min) PCI ISA MEM space 0xC4000000 448MB (max) PCI MEM space 0xFA000000 2MB NVRAM, Board Control Registers 0xFA200000 16KB CPV internal memory resources, DPRAM 0xFA210000 64KB PCI Bus Bridge registers (QSPAN) 0xFC000000 1MB (min) FLASH memory 0xFE000000 128KB (min) Boot ROM
The diagram below shows the Data Parameter Ram layout for the VxWorks
configuration:
----------------------------- DPRAM base (address = IMMR + 0x2000)
| 0x200 (512) bytes |
| I2C/SCC1 conflict |
| microcode patch part 1 |
|---------------------------| end microcode patch (0x2200)
| 8 bytes per descriptor | UART Tx Buffer Descriptor (0x2200)
|===========================|
| 16 descriptors @ | UART Rx Buffer Descriptors (0x2210)
| 8 bytes per descriptor |
|===========================| end UART Rx BDs (0x2290)
| 80 hex bytes allowed | UART Tx Buffer (0x2300)
|===========================|
| one receive char/buffer | UART Rx Buffer (0x2380)
|===========================|
| 16 bytes allowed | I2C Buffer Descriptors (0x2400)
|---------------------------|
| 32 bytes allowed | I2C Buffer (0x2410)
|===========================|
| 256 bytes allowed | SROM temp. buffer (0x2600)
|---------------------------|
| 256 bytes allowed | SROM temp. system values (0x2700)
|===========================|
| 512 bytes | romInit temp. stack frame (0x2D00)
|===========================|
| 0x200 (512) bytes | microcode patch (0x2F00)
| I2C/SCC1 conflict |
| microcode patch part 2 |
|===========================|
| 66 hex bytes of parameter | SCC2 Parameter Area (0x3d00) UART
| info incl. Rx and Tx BD |
| pointers, func codes etc. |
|===========================|
| 3A hex bytes of parameter | SMC1 Parameter Area (0x3e80) UART
| info including Rx and Tx |
| BD pointers, func codes |
| etc... |
|---------------------------|
The PowerPC architecture defines a series of 48 vectored exceptions (see the "PowerPC Microprocessor Family: The Programming Environments" for details). Of these, all but two are handled by the synchronous exception handler: External Interrupt and Decrementer which are handled by the asynchronous exception handler.By default, the exception handling task excTask( ) handles all synchronous exceptions. It reports an exception and terminates the offending task.
Of the 48 exceptions, only five are of immediate interest:
Machine Check - exceptions from probed addresses handled here. Data Access - exceptions from unmapped MMU addresses handled here. Alignment - alignment exceptions handled here. Decrementer - used as system clock interrupt. External Interrupt - off-CPU interrupts arrive here.The Machine Check exception is used by the vxMemProbe( ) routine. It is not used in any other context. By default it is handled by excTask( ).The Data Access and Alignment exceptions are by default handled by excTask( ). The vxMemProbe routine installs it's own handlers here while probing.
The Decrementer and External Interrupt exceptions each have their own C service stubs. The Decrementer exception is used solely by the system clock routine to service the periodic tick interrupts.
The External Interrupt exception stub is connected at startup to the system- maintained interrupt vector table and BSP-specific intConnect( ) routine. All SIU, CPM, PCI, and ISA interrupts are vectored through this table.
All other exceptions are handled by default by the exception handler task, excTask( ).
The system interrupt vector table has 256 entries. Vectors for the various devices on the busses are assigned hierarchically as follows:
Vector# Assigned to ------- --------------------------------------------------------------- 00 - 0f SIU interrupts 10 - 1f RESERVED 20 - 3f CPM interrupts 40 - 5f USER DEFINED 60 - 72 Dec2155x interrupts 73 - ff USER DEFINEDThe specific SIU vector number assignments are:
Vector# Interrupt Assigned to ------- -------- -------------------------------------------------- 0x0 IRQ0 Power Fail, non-maskable intr 0x1 LEVEL0 real-time clock 0x2 IRQ1 Battery low warning 0x3 LEVEL1 periodic interrupt timer 0x4 IRQ2 QSPAN interrupt 0x5 LEVEL2 timebase counter 0x6 IRQ3 PMC1 Interrupt C, PMC2 Interrupt B, QSPAN (PCI) 0x7 LEVEL3 Fast Ethernet (FEC - on the MPC860T chip) 0x8 IRQ4 PMC1 Interrupt B, PMC2 Interrupt A 0x9 LEVEL4 CPM controller 0xA IRQ5 PMC1 Interrupt A, PMC2 Interrupt D 0xB LEVEL5 Unused 0xC IRQ6 PMC1 Interrupt D, PMC2 Interrupt C, DEC21554 0xD LEVEL6 parallel interface port 0xE IRQ7 stop/abort 0xF LEVEL7 UnusedNote: On boards using an MPC860T chip (containing the FEC), the IRQ7 line is shared with the MII_TX_CLK signal. When the ETHER_EN bit is set in the Ethernet Control Register of the FEC, the IRQ7 line will fire incessantly unless the IRQ7 interrupt mask bit is cleared in the SIU Interrupt Mask Register.The specific CPM vector number assignments are:
Vector# Assigned to ------- --------------------------------------------------------------- 0x20 Error 0x21 Parallel I/O [4] 0x22 Parallel I/O [5] 0x23 SMC 2/PIP 0x24 SMC 1 0x25 SPI 0x26 Parallel I/O [6] 0x27 Timer 4 0x28 reserved 0x29 Parallel I/O [7] 0x2A Parallel I/O [8] 0x2B Parallel I/O [9] 0x2C Timer 3 0x2D reserved 0x2E Parallel I/O [10] 0x2F Parallel I/O [11] 0x30 I2C 0x31 Risc Timer Table 0x32 Timer 2 0x33 reserved 0x34 IDMA2 0x35 IDMA1 0x36 SDMA bus error 0x37 Parallel I/O [12] 0x38 Parallel I/O [13] 0x39 Timer 1 0x3A Parallel I/O [14] 0x3B reserved 0x3C reserved 0x3D SCC2 0x3E SCC1 0x3F Parallel I/O [15]The specific DEC2155X interrupts are:
Vector# Assigned to ------- --------------------------------------------------------------- 0x60 DEC2155X DOORBELL 0 0x61 DEC2155X DOORBELL 1 0x62 DEC2155X DOORBELL 2 0x63 DEC2155X DOORBELL 3 0x64 DEC2155X DOORBELL 4 0x65 DEC2155X DOORBELL 5 0x66 DEC2155X DOORBELL 6 0x67 DEC2155X DOORBELL 7 0x68 DEC2155X DOORBELL 8 0x69 DEC2155X DOORBELL 9 0x6a DEC2155X DOORBELL 10 0x6b DEC2155X DOORBELL 11 0x6c DEC2155X DOORBELL 12 0x6d DEC2155X DOORBELL 13 0x6e DEC2155X DOORBELL 14 0x6f DEC2155X DOORBELL 15 0x70 DEC2155X POWER MANAGEMENT 0x71 DEC2155X I2O 0x72 DEC2155X PAGE CROSSING
The Serial port selections supported are via the SMC1 or the SCC2 interface in the MPC860 communications processor module.
The serial port can be configured in one of two ways:
- 1)
- As SMC1 (part of the MPC860 communications processor module). To configure this way, set SERIAL_PORT to SERIAL_PORT_SMC in "config.h".
- 2)
- As SCC2 (part of the MPC860 communications processor module). To configure this way, set SERIAL_PORT to SERIAL_PORT_SCC in "config.h".
SCSI is not supported as a standard feature on the CPV series boards.
CPV boards with an MPC860T processor provide a 10Base-T/100BaseTX Fast Ethernet Controller module. This replaces the Ethernet interface used via the SCC1 port. The FEC module will automatically select the fatest transfer rate available.Each CPV board is assigned a unique Media Access Control (ethernet) address. The address is of the form 0x08003EXXXXXX, where 0x08003E is the identification for Motorola MCG and 0xXXXXXX is a unique serial number assigned to each CPV board by MCG. The MAC address is read out of SROM during sysHwInit.
Does not apply.
The PCI bus is fully supported under rev 2.1 of the standard. All configuration space accesses are made with BDF (bus #, device #, function #) format calls in the pciConfigLib module.
CPU to PCI Memory Map (default base addresses) CPU PCI Max Size Access to -------------------------------------------------------------- 0x80000000 0x00000000 64 KB ISA I/O space 0x80010000 0x00010000 511 MB PCI I/O space 0xC0000000 0x00000000 64 MB ISA MEM space 0xC4000000 0x04000000 448 MB PCI MEM space PCI to CPU Memory Map PCI CPU Max Size Access to ----------------------------------------------------------- 0x80000000 0x00000000 2 GB local DRAM
The CPU to PCI Memory Map can be altered by changing the values of the PCI_MSTR_xxx defines in config.h. In specifying the CPU base addresses that will translate to the PCI bus, only the PCI I/O base can be altered. The PCI Memory space will automatically be set based on the value from ISA_MSTR_IO_LOCAL (it will be calculated as ISA_MSTR_IO_LOCAL + 0x40000000). This is due to the fact that the second most significant bit of the address lines from the CPU is hardwired to the Image Select (IMSEL) line of the QSPAN chip. It is also important to note that this bit must not be set when used for the PCI I/O base address.
The address being translated to on the PCI bus can be specified for Memory space only. The define "PCI_MSTR_MEM_BUS" would be set with the value to be used on the PCI bus. The tranlation of PCI I/O space must be to zero based addressing on the PCI bus due to legacy issues with ISA devices.
Sizing windows can be set for CPU to PCI address translations. The first set specify the window for CPU access to the QBUS, the second specifies the window for QBUS access to the individual PCI space via the QSPAN. The size for CPU access to the QBUS is set by the "PCI_MSTR_IO_SIZE" define. This value is used for both I/O and MEM space access to the QBUS, due to the fact that they share a CPU access window. The size value will determine how much each space will have available for access to the QBUS from its respective CPU base address. The second sizing windows setup the 4 PCI/ISA windows defined in the Page Table Entries. These windows determine where access to PCI I/O amd Mem space and ISA I/O and Mem space will occur. They also define the true amount of space accessible for each space (from a programming point of view ). Care must be taken when expanding the PCI I/O and PCI MEM window sizes, they require 64KB of local memory per 8MB of PCI space mapped.
The total size for (PTE_ISA_IO_SIZE + PTE_PCI_IO_SIZE) must be less than or equal to PCI_MSTR_IO_SIZE. The total size for (PTE_ISA_MEM_SIZE + PTE_PCI_MEM_SIZE) must be less than or equal to PCI_MSTR_IO_SIZE.
The third set of windows are configured by modifying a QSPAN_QBSI_xxxx code for the defines "QSPAN_MSTR_IO_SIZE" and "QSPAN_SLV_MEM_SIZE" and specifies how much each of address space will actually be decoded onto the PCI bus by the QSPAN chip. The size for these two defines does not have to be the same. The size should not exceed the value for "PCI_MSTR_IO_SIZE".
The only access from the PCI to CPU space is from PCI Memory space. The define "PCI_SLV_MEM_BUS" is the base address as seen on the PCI bus, and the "PCI_SLV_MEM_LOCAL" is the base address of local memory in CPU space. The defines "PCI_SLV_MEM_SIZE" and "QSPAN_SLV_MEM_SIZE" are used in determining how much CPU space is accessible, and should be set to the same sizes.
The QSPAN CPU to PCI bridge chip provides an interface between the CPV processor bus (called the QBus) and the PCI Bus. Revisions 1.0 and 1.1 of the QSPAN chip could not support normal termination of PCI configuration cycles. This requires the installation of a machine check handler every time a PCI configuration space access is made, otherwise the kernel will hang. Starting with the revision 1.2 QSPAN, a new bit field (MA_BE_D) has been added to the MISC_CTL register. Setting this bit will cause PCI configuration reads and writes to appear as normal terminations on the QBus, eliminating the need for the special handling.
The 1.2 revision has also added support for QBus Master burst writes and prefetch reads. These will not be implemented as part of the QSPAN driver. The QSPAN 1.2 addendum recommends that burst write not be used when using the UPM tables for memory access, which this BSP does implement.
The supported boot devices are:
motfec - ethernet (10baseT or 100baseT) sm - share memoryMotorola's EPPC1-Bug can be used to download and run VxWorks. Consult the respective user's manuals for details.
The boot methods are affected by the boot parameters. If no password is specified, RSH (remote shell) protocol is used. If a password is specified, FTP protocol is used or, if the flag is set, TFTP protocol is used.
The following will produce a binary formatted file to be downloaded to the CPV using EPPC-Bug.
make clean make bootrom.bin cp bootrom.bin /tftpboot/cpv3060/bootrom.bin chmod 666 /tftpboot/cpv3060/bootrom.binUsing EPPC-Bug on the CPV, the following instructions will flash the boot.bin (binary image of the bootrom file) into the SOLDERED FLASH.To install the boot.bin file in the SOLDERED FLASH parts:
- 1)
- Before you power-up the CPV, make sure the ROM/FLASH jumper (W2) is installed across pins 1 and 2 to select running from the socketed flash.
With W2 installed across pins 1 and 2, the:
- Socketed ROM has an address of 0xFE000000
- Soldered FLASH has an address of 0xFC000000If W2 is installed across pins 2 and 3, the above addresses are swapped. The current, selected device (ROM or FLASH) always is located at 0xFE000000.
- 2)
- At the EPPCBug prompt, setup the network transfer from a tftp host using niot. To use niot, the Client IP Address, Server IP Address, and Gateway IP Address must be setup for the user's specific environment:
EPPC-Bug>niot Controller LUN =00? 20 Device LUN =00? Node Control Memory Address =003C8000? Client IP Address =123.123.10.100? 123.321.12.123 Server IP Address =123.123.18.105? 123.321.21.100 Subnet IP Address Mask =255.255.255.0? Broadcast IP Address =255.255.255.255? Gateway IP Address =123.123.10.254? 123.321.12.254 Boot File Name ("NULL" for None) =? . Update Non-Volatile RAM (Y/N)? y EPPC-Bug>- 3)
- The file is transferred from the tftp host to the target board using the niop command. The File Name must be set to the location of the binary file on the tftp host.
The binary file must be stored in the directory identified for tftp accesses, but the File Name is a relative path and may not need to include the /tftpboot directory name:
EPPC-Bug>niop Controller LUN =20? Device LUN =00? Get/Put =G? File Name =? cpv3060/bootrom.bin Memory Address =00004000? Length =00000000? Byte Offset =00000000? EPPC-Bug>- 4)
- After the file is loaded onto the target, use the pflash command to put it into the soldered FLASH parts (W2 installed across pins 1 and 2):
EPPC-Bug>pflash 4000:83fff fc000100
When executing "pflash", you may see eight Data Miscompare Statements in the verify-phase, this is normal and requires no action.
- 5)
- Power down the board, then switch the W2 jumper to
pins 2 - 3, and re-apply power to the board.
The SDRAM controller setup is only performed by the boot program. VxWorks doesn't re-initialize the SDRAM controller when it is executed. The following are the current SDRAM speed configurations supported:
60ns @ 50 MHz 60ns @ 100 MHzTo support a different configuration the UpmTable table located in romInit.s file of the cpv3060 BSP must be changed.
Dynamic sizing of the memory available on the CPV board can be accomplished by enabling the define for LOCAL_MEM_AUTOSIZE in config.h and then rebuilding the kernel. This will automatically make available the full range of memory on the board.
One of two types of clock input is used on the board. Either a 32768KHz crystal or a 1:1 oscillator is used as the CPV primary clock source. The boot ROM and kernel detect and configure themselves dynamically to support the configured clock. No special user configuration is required.
This section describes miscellaneous information about the BSP.
1. The parameter RAM for SCC1 overlaps the parameter RAM for I2C. This would normally prevent the ethernet and I2C from working concurrently. A microcode patch is installed by i2cMcp.c during kernel initialization, to work around this problem. It relocates the I2C parameter RAM to the location occupied by IDMA1, which is not used for any other purpose. Thus making both SCC1 and I2C operate concurrently.
2. A large switch statement, ( 16 cases for the one tested ) fails to execute properly when running in ROM. This appears to be an 860 specific problem, and may only occur with code running in ROM. When the same code ( the bootrom ) was executed with a debugger in RAM, the error did not occur.
A small switch statement does not exhibit the same failure. The reason for this is the way switch statements are compiled into assembly code. For small switch statements, the code is compiled as if it were a series of if-then-else statements. For a large switch statement, a jump table is created. This jump table is the reason for the failure in the ROM code.
3. In order to use the cpv3060 in a shared memory backplane configuration with mcp750 and/or mcpn750 boards, the mcp750/mcpn750 Compact PCI backpanel networking patch must be installed on those boards first. This will allow the 750 boards to recognize the version of the DEC21554 Drawbridge chip on the cpv3060. Contact your Motorola Sale Representative in order to get a copy of this patch.
The diagram below shows jumpers relevant to VxWorks configuration.
^ ^ | To Compact PCI | Backplane ____________________________________________________________________________ | | | | | | | J5 | | J3 | | J1 | |______________|_____________|_____________|_______________|_______________| | | | =========== =========== =========== =========== | | | | =========== =========== =========== =========== | | PMC slot PMC slot | | | | | | | | | | | | | | +-----+ | | | | | | | | | | +-----+ | | U21 | | | | . | | : (W2) | | | | | | | | | | | | | | | |______.......................___.......................____----_____----__| PCI Mezzanine Card PCI Mezzanine Card 10/100 Com1 Cutout Cutout base T Front of BoardKey:
U21 - Socketed Rom Bank, EPPC1Bug installed
W2 - three-pin vertical jumper (selects Socketed/Soldered ROM)
Tornado User's Guide: Getting Started, VxWorks Programmer's Guide: Configuration
Motorola CPV3060 Programmer's Reference Guide, Motorola Computer Group Online Documentation, http://library.mcg.mot.com/mcg/boards