VxWorks BSP Reference : ads8260

ads8260

NAME

ads8260 - Motorola MPC8260ADS

INTRODUCTION

This reference entry provides board-specific information necessary to run VxWorks for the ads8260 BSP.

The BSP will work with the rev PILOT of the ADS8260 board. The default rev is PILOT, which is turned on by the macro BOARD_REV_PILOT in config.h.

BOOT ROMS

No VxWorks Boot ROM is provided with this BSP release. Nevertheless VxWorks boot code is working if downloaded into the SIMM Flash ROM.

VxWorks boot code can be programmed in to Flash using one of the following methods:

1. Using Macraigor Raven

Using the Macraigor Raven (www.macraigor.com), and their OCD Commander host-based software a bootrom image can be read from the host and programmed into Flash Rom, as detailed below:

On the host, prepare a hex image of the bootrom. On a Unix host:

        make bootrom_uncmp.hex

Install the Raven connector through a parallel port onto your host, and power it on. Connect the COP interface cable from the Raven into the ADS board's JTAG/COP connector.

Once all the connections have been made, power up the ADS board and start the OCD Commander executable on the host.

1. Execute the reset command to initialize the board:

        > RESET

2. Click FLASH PGM. Wait for the flash programmer to come up.

3. Click Program. Wait for the programming menu.

4. Click Browse and select the bootrom_uncmp.hex file.

5. Select "Erase Target Flash Sectors Before Programming".

6. Change the "Start Programming at Flash Address:" value to 0xfff00000.

7. Click Program. The software will erase the flash, then program it, and finally will say Program/Verify Complete.

2. Using vxWorks

Booting VxWorks as detailed below, and then using VxWorks to read the bootrom image from a host and to program it into Flash Rom

This is explained below:

1. Boot VxWorks as detailed below

2. Configure and start the Tornado target server on the host.

3. On the host, prepare a hex image of the bootrom. On a Unix host:

        make bootrom_uncmp.bin
        cp bootrom_uncmp.bin /tmp
        ls -l /tmp/bootrom_uncmp.bin

Note the number of bytes given by the last step

4. Using a VxWorks shell, read and program the image. Replace the number of bytes (359044 below) with the size of your image. Make sure the allocated buffer is large enough:

        sysFlashErase 0
        fd1 = open ("/tmp/bootrom_uncmp",2,0)
        p1 = malloc (0x100000)
        read (fd1, p1, 359044)
        sysFlashWrite (p1, 359044, 0,0)

Note that the offset on the PILOT rev board will have to be (0xfff00000 - FLASH_ADRS). See ROM considerations below.

5. At this point the VxWorks bootrom is programmed into Flash rom. Resetting the board should yield the familiar VxWorks boot screen.

Jumpers on PILOT board revision

The baud rate generator assumes a 40 MHz or 66 MHz system clock and a CPM multiplication factor of 2. Although the PILOT board supports reading the Hard Reset Configuration Word from Flash or from the BCSR, the currently shipping Pilot Board has a processor XPC8260 rev. 0.2, which does not support reading the Flash at Power-on or Hard reset and so must be set to use BCSR. This setting and the CPM multiplication factor is programmed on DS1, as follows:

Label	Position
FLASH/BCSR	Off
MODCKH 0	On
MODCKH 1	Off
MODCKH 2	On
MODCKH 3	Off
MODCK 1	Off
MODCK 2	Off
MODCK 3	Off

If the system clock is 33 MHz then the DIP switch MODCKH 1 (position 3) should be set to Off.

On revision PILOT of the ADS8260 board, there is a new JTAG machine inserted in front of the MPC8260's COP/JTAG port to provide fast download capability for the ADS. Via J5 it is possible to bypass the new JTAG machine to be compatible with the ENG rev of the board. In the tested configuration, a jumper is placed between positions 1-2 of J5 to enable the new JTAG machine.

FEATURES

Supported Features (PILOT board revisions)

SCC1 and SCC2 as a UART

FCC2 as an Ethernet device supporting 10BaseT and 100BaseT protocol

Interrupt Controller

System Clock

Baud Rate Generators as required for SCC1 and SCC2

16 MByte SDRAM DIMM on 60x bus (32 and 64 MByte configurations have not been tested)

DMA as required only for SCC1, SCC2, and FCC2

Auxiliary clock and timestamp clock

8 MByte Flash module (16 and 32 MByte configurations have not been tested)

Flash read and write capability

Instruction and Data caches

Unsupported Features (PILOT board revisions)

virtual DMA

Parallel Ports

Baud Rate Generators not used by supported devices

SPI

I2C

4MByte SDRAM on local bus.

Reset capability or options

SCC1 and SCC2 in any mode other than UART

SCC3 and SCC4

ATM, Transparent, or HDLC protocols on FCC2

FCC1 and FCC3

MCC1 and MCC2

SMC1 or SMC2

Any of the eight TDM interfaces

Support for the PCI bridge (hardware not available yet)

Support for the L2 cache (hardware not available yet)

Support for the two 96 DIN connectors (Voyager Tools Board connector and Expansion connector) which bring out all pins on the MPC8260 chip

Feature Interactions

None known

HARDWARE DETAILS

This section documents the details of the device drivers and board hardware elements.

Devices

The chip drivers included are:

    m8260Flash.c - flash memory driver
    m8260Sio.c - serial driver
    m8260IntrCtl.c - interrupt controller driver
    m8260Timer.c - timer driver
    motFccEnd.c - FCC Ethernet END driver
    miiLib.c - Media Independent Interface library

The BSP configures both SCC1 and SCC2 as UART devices. SCC1 is used as a console device. FCC2 is used as an ethernet port.

Memory Maps

The following table describes the ads8260 default memory map:

Start	Size	End	Access to
0x0000_0000	16MB	0x00FF_FFFF	SDRAM DIMM on 60X bus
0x0100_0000	48MB	0x03FF_FFFF	Unused (partially used when optional 32MB DIMM
			is installed, and fully used when optional 64MB DIMM
			is installed in place of standard 16MB DIMM)
0x0400_0000	4MB	0x043F_FFFF	Soldered SDRAM on local (1) bus (unsupported)
0x0440_0000	1MB	0x044F_FFFF	Unused
0x0450_0000	32KB	0x0450_7FFF	Board Control and Status Registers
			(BCSR0 through BCSR7 on PILOT revision)
0x0450_8000		0x045F_FFFF	Unused
0x0460_0000	32KB	0x0460_7FFF	ATM (unsupported)
0x0460_8000		0x046F_FFFF	Unused
0x0470_0000	64KB	0x0471_FFFF	MPC 8260 Internal Memory
			(see MPC8260 PowerQUICC II User's Manual,
			Chapter 3, Memory Map, and
			Chapter 13, CPM Overview, for further details,
			and see Parameter Ram below)
0x0472_0000		0xFCFF_FFFF	Unused
0xFD00_0000	32MB	0xFFFF_FFFF	Flash SIMM (size optional)

The following table describes the ads8260 default usage of the MPC8260's internal Parameter Ram, sometimes also called Data/Parameter Ram or DPRAM:

Start	Size	End	Description
0x0470_0000	8 bytes	0x0470_0007	SCC1 Receive Buffer Descriptor
0x0470_0000	2 bytes	0x0470_0001	SCC1 Receive Buffer Status
0x0470_0002	2 bytes	0x0470_0003	SCC1 Receive Buffer Length
0x0470_0004	4 bytes	0x0470_0007	pointer to SCC1 Receive Buffer
0x0470_0008	8 bytes	0x0470_000F	SCC1 Transmit Buffer Descriptor
0x0470_0008	2 bytes	0x0470_0009	SCC1 Transmit Buffer Status
0x0470_000A	2 bytes	0x0470_000B	SCC1 Transmit Buffer Length
0x0470_000C	4 bytes	0x0470_000F	pointer to SCC1 Transmit Buffer
0x0470_0040	1 bytes	0x0470_0040	SCC1 Receive Buffer
0x0470_0060	1 bytes	0x0470_0060	SCC1 Transmit Buffer
0x0470_0100	8 bytes	0x0470_0107	SCC2 Receive Buffer Descriptor
0x0470_0100	2 bytes	0x0470_0101	SCC2 Receive Buffer Status
0x0470_0102	2 bytes	0x0470_0103	SCC2 Receive Buffer Length
0x0470_0104	4 bytes	0x0470_0107	pointer to SCC2 Receive Buffer
0x0470_0108	8 bytes	0x0470_010F	SCC2 Transmit Buffer Descriptor
0x0470_0108	2 bytes	0x0470_0109	SCC2 Transmit Buffer Status
0x0470_010A	2 bytes	0x0470_010B	SCC2 Transmit Buffer Length
0x0470_010C	4 bytes	0x0470_010F	pointer to SCC2 Transmit Buffer
0x0470_0140	1 bytes	0x0470_0140	SCC2 Receive Buffer
0x0470_0160	1 bytes	0x0470_0160	SCC2 Transmit Buffer

The following table describes the default VxWorks macros which are used to address memory

Macro Name	Macro Definition	Description
LOCAL_MEM_LOCAL_ADRS	0x0000_0000	Base of RAM
RAM_LOW_ADRS	LOCAL_MEM_LOCAL_ADRS + 0x0001_0000
	VxWorks image loaded here. Stack grows down from this address.
RAM_HIGH_ADRS	LOCAL_MEM_LOCAL_ADRS + 0x00d0_0000
	VxWorks bootrom loaded here.
LOCAL_MEM_SIZE	0100_0000	Default 16 MBytes of RAM
BCSR_BASE_ADRS	0450_0000	Default location of Board Control and Status Registers on PILOT rev
BCSRS_SIZE	0001_0000	64 KBytes on PILOT rev
DEFAULT_IMM_ADRS	0470_0000	Default location of MPC 8260 Internal Memory Map
IMM_SIZE	0x20000	128K Internal Memory Map Size
ROM_BASE_ADRS	0xFFF0_0000	Base address of ROM on PILOT rev
ROM_TEXT_ADRS	ROM_BASE_ADRS + 0x100
	Text must start after vector table
ROM_WARM_ADRS	ROM_TEXT_ADRS + 8
	Warm Reboot Entry Address
ROM_SIZE	0x0010_0000	Default 1 MByte of ROM on PILOT rev (see ROM considerations)

Shared Memory

NA

Interrupts

The following table describes the relationship between the interrupt number, interrupt vector, and the interrupt bit position in the SIU Interrupt Mask Register (SIMR_H and SIMR_L). Also described is the mask to use to enable all interrupts of a higher priority. See m8260Int.c for usage.

Default				Mask to Enable
Interrupt	Interrupt	Interrupt	SIMR	Higher Priority Interrupts	Interrupt
Priority	Number	Vector	Mask	SIMR_H	SIMR_L	Source
						HIGHEST PRIORITY
1	16	0x10	H 0x00000004	0000_0000	0000_0000	TMCNT
2	16	0x10	H 0x00000004	0000_0000	0000_0000	TMCNT
3	17	0x11	H 0x00000002	0000_0004	0000_0000	PIT
4	reserved
5	19	0x13	H 0x00004000	0000_0006	0000_0000	IRQ1
6	27	0x20	L 0x80000000	0000_4006	0000_0000	FCC1
7	28	0x21	L 0x40000000	0000_4006	8000_0000	FCC2
8	29	0x22	L 0x20000000	0000_4006	C000_0000	FCC3
9	inactive
10	unused
11	31	0x24	L 0x08000000	0000_4006	E000_0000	MCC1
12	32	0x25	L 0x04000000	0000_4006	E800_0000	MCC2
13	inactive
14	inactive
15	20	0x13	H 0x00002000	0000_4006	EC00_0000	IRQ2
16	21	0x14	H 0x00001000	0000_6006	EC00_0000	IRQ3
17	22	0x15	H 0x00000800	0000_7006	EC00_0000	IRQ4
18	23	0x16	H 0x00000400	0000_7806	EC00_0000	IRQ5
19	unused
20	35	0x28	L 0x00800000	0000_7C06	EC00_0000	SCC1
21	36	0x29	L 0x00400000	0000_7C06	EC80_0000	SCC2
22	37	0x2A	L 0x00200000	0000_7C06	ECC0_0000	SCC3
23	38	0x2B	L 0x00100000	0000_7C06	ECE0_0000	SCC4
24	inactive
25	inactive
26	inactive
27	inactive
28	unused
29	40	0x30	H 0x00010000	0000_7C06	ECF0_0000	PC15
30	12	0x0C	L 0x00000010	0001_7C06	ECF0_0000	Timer 1
31	41	0x31	H 0x00020000	0001_7C06	ECF0_0010	PC14
32	unused
33	42	0x32	H 0x00040000	0003_7C06	ECF0_0010	PC13
34	10	0x0A	L 0x00000040	0007_7C06	ECF0_0010	SDMA Bus Error
35	6	0x06	L 0x00000400	0007_7C06	ECF0_0050	IDMA1
36	unused
37	43	0x33	H 0x00080000	0007_7C06	ECF0_0450	PC12
38	44	0x34	H 0x00100000	000F_7C06	ECF0_0450	PC11
39	7	0x07	L 0x00000200	001F_7C06	ECF0_0450	IDMA2
40	13	0x0D	L 0x00000008	001F_7C06	ECF0_0650	Timer 2
41	45	0x35	H 0x00200000	001F_7C06	ECF0_0658	PC10
42	unused
43	unused
44	3	0x03	L 0x00002000	003F_7C06	ECF0_0658	RISC Timer Table
45	1	0x01	L 0x00008000	003F_7C06	ECF0_2658	I2C
46	unused
47	46	0x36	H 0x00400000	003F_7C06	ECF0_A658	PC9
48	47	0x37	H 0x00800000	007F_7C06	ECF0_A658	PC8
49	24	0x18	H 0x00000200	00FF_7C06	ECF0_A658	IRQ6
50	8	0x08	L 0x00000100	00FF_7E06	ECF0_A658	IDMA3
51	25	0x19	H 0x00000100	00FF_7E06	ECF0_A758	IRQ7
52	14	0x0E	L 0x00000004	00FF_7F06	ECF0_A758	Timer 3
53	unused
54	unused
55	48	0x38	H 0x01000000	00FF_7F06	ECF0_A75C	PC7
56	49	0x39	H 0x02000000	01FF_7F06	ECF0_A75C	PC6
57	50	0x3A	H 0x04000000	03FF_7F06	ECF0_A75C	PC5
58	15	0x0F	L 0x00000002	07FF_7F06	ECF0_A75C	Timer 4
59	unused
60	51	0x3B	H 0x08000000	07FF_7F06	ECF0_A75E	PC4
61	unused
62	9	0x09	L 0x00000080	0FFF_7F06	ECF0_A75E	IDMA4
63	2	0x02	L 0x00004000	0FFF_7F06	ECF0_A7DE	SPI
64	52	0x3C	H 0x10000000	0FFF_7F06	ECF0_E7DE	PC3
65	53	0x3D	H 0x20000000	1FFF_7F06	ECF0_E7DE	PC2
66	4	0x04	L 0x00001000	3FFF_7F06	ECF0_E7DE	SMC1
67	unused
68	5	0x05	L 0x00000800	3FFF_7F06	ECF0_F7DE	SMC2
69	54	0x3E	H 0x40000000	3FFF_7F06	ECF0_FFDE	PC1
70	55	0x3F	H 0x80000000	7FFF_7F06	ECF0_FFDE	PC0
71	unused
72	unused
73	reserved
						LOWEST PRIORITY

Serial Configuration

SCC1 and SCC2 are configured as UART devices with 8 data bits, 1 stop bit, hardware handshaking, and parity disabled.

SCSI Configuration

There is no SCSI interface on this board.

Network Configuration

FCC2 is configured as an Ethernet port

VME Access

NA

PCI Access

There is no PCI interface on this board.

Boot Devices

motFcc

Boot Methods

Ethernet

Load image via Macraigor Raven and invoke via "OCD Commander"

ROM Considerations for PILOT board revision

The actual size of Flash memory on this board is 8MB (optionally 16MB or 32MB) starting at (0xffffffff - FLASH_SIZE).

The system exception vector table is placed at 0xfff00000, so boot-up code has to be programmed at this location.

The BSP was tested with both compressed and uncompressed boot roms programmed at this location. If there is not enough space for the bootrom image or a vxWorks standalone image is required to be in ROM, this can be achieved by placing a stub that jumps to start of flash memory. This requires either a compiler which can provide 2 text segments or manually programming the stub and the main image at different locations without overwriting each other.

SPECIAL CONSIDERATIONS

This section describes miscellaneous information that the user needs to know about the BSP.

Delivered Objects

Make Targets

Bootrom_uncmp, vxWorks and vxWorks.st are delivered. All other make targets are untested. For PILOT revision of board, bootrom (compressed) is also tested.

Special Routines

None

Serial Connections

Most VxWorks BSPs do not use hardware handshaking in the serial interface, and thus a simple 3 wire connection is commonly used. The MPC8260 ADS BSP does use hardware handshaking and this requires a full 8 pin interface. Standard molded RS-232 cables have been shown to work, possibly requiring a null modem adapter.

See also "Known Problems" below.

Ethernet Address

The MPC8260 ADS boards do not have a unique Ethernet hardware address assigned to each board. A unique address is absolutely necessary if the user wishes to connect the board to a network. Thus, the user must provide a suitable 6 byte Ethernet address for each board used on a network. The address is programmed by changing the sysFccEnetAddr character array in the file sysLib.c. The first three bytes (0x08, 0x00, 0x3e) are a Motorola-specific prefix that should be kept as-is. The user must change the last three bytes from 0x03, 0x02, 0x01 to three unique bytes (i.e., bytes not used by any other Motorola Ethernet connection on your net). Check with your system administrator if you do not know this information.

Documentation Errata

Note that in the Motorola MPC8260 PowerQUICC II ADS User's Manual the size of the MPC8260's Internal MAP is incorrectly stated. it is stated correctly in the Motorola MPC8260 PowerQUICC II User's Manual as 128K bytes.

Known Problems

Serial driver transmitter hangs if receiver is hit too rapidly; however receiver continues to function.

Initialization Values

The VxWorks bootrom completely initializes the board. On the other hand, VxWorks does not reinitialize many registers. Thus, when the VxWorks image is loaded via the Macraigor Raven and vbug, most values are initialized by the debugger and not by VxWorks. For a list of initialized values, refer to the "VBUG PowerQUICC II Debugger"

.bp

Tested Configuration

The MPC8260 chip, the MPC8260 ADS, and the host-based software as purchased might differ from the ones used to develop this bsp. Thus, we document the configuration that was used to develop the BSP:

Board Markings:

MPC8260 ADS
REV. PILOT  (for PILOT revision of board)

CPU Chip Markings:

PPC8260ZU
2J24M CREAA9927 HKG (for PILOT rev)

SYSCLK oscillator:

40 MHz 

DIP Switches for PILOT rev:

PON. RST. CONF. (DS1):

Label	Position
FLASH/BCSR	Off
MODCKH 0	On
MODCKH 1	Off
MODCKH 2	On
MODCKH 3	Off
MODCK 1	Off
MODCK 2	Off
MODCK 3	Off

SDRAM CONF. ADD. (DS2) for PILOT rev:

Label	Position
SA2	Off
SA1	Off
SA0	Off
RESERVED	Off

SDRAM Interleave Modes

According to the latest manual, bit 0 of PSDMR is "PBI", Page Based Interleave. This is true for silicon rev A, which is not yet available. For the silicon that is currently available, this bit is reserved and should be 0, as the sample initialization code indicates.

Silicon before Rev A supports only Bank Based Interleave. Page Based Interleave will be available only on silicon rev A and beyond.

SYSCLK Frequency

Most Motorola sample code and documentation refers to a default system clock frequency of 66 MHz; However, problems occur at this frequency, and thus the ADS is normally delivered with a 40 MHz oscillator.

BOARD LAYOUT

The diagram below shows jumpers and connectors relevant to VxWorks configuration for PILOT revisions of the board.

___________________________________________________________________________
|  RS-232 1 (upper)    P5                                                 |
|  RS-232 2 (lower)    COP-JTAG
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
|                                                                         |
| P2 - Ethernet                                                           |
|                                                                   P19   |
|                                                                  Power  |
|                            -------------                        ________|
|     P4 - CPM expansion     |            |  P16 - SYS expansion  |
|____________________________|            |_______________________|

Key:
    X  vertical jumper installed
    :  vertical jumper absent
    -  horizontal jumper installed
    "  horizontal jumper absent
    0  switch off
    1  switch on
    U  three-pin vertical jumper, upper jumper installed
    D  three-pin vertical jumper, lower jumper installed
    L  three-pin horizontal jumper, left jumper installed
    R  three-pin horizontal jumper, right jumper installed

SEE ALSO

Tornado User's Guide: Getting Started, VxWorks Programmer's Guide: Configuration, VxWorks Programmer's Guide: Architecture Appendix

BIBLIOGRAPHY

MPC8260 ADS User's Manual MPC8260ADS User's Manual, for PILOT revision bd, 11/1999 PowerQUICC II User's Manual, rev. 0 MPC8260 PowerQUICC II User's Manual Errata, rev. 0 MPC8260 Design Checklist PowerPC Microprocessor Family: The Programming Environments for 32-bit Microprocessors MPCFPE32B/AD MPC603e & EC603e RISC Microprocessors User's Manual MPC603EUM/AD VBUG PowerQUICC II Debugger

WEB RESOURCES

Much of the Motorola documentation can be found on line. The following URL was correct at the time of writing; however, Motorola may move these pages without notifying Wind River Systems.

http://www.mot.com/SPS/RISC/netcomm/prod/eppc/MPC8260.html

Contains the following:

    MPC8260 Product Briefs
    MPC8260 User's Manuals
    MPC8260 Hardware Specifications
    MPC8260 Errata
    MPC8260 Third Party Support
    MPC8260 Training Materials

http://www.mot.com/netcomm

Contains the following:

    MPC8260ADS User's Manual, for PILOT revision bd, 11/1999

http://www.mot.com/SPS/RISC/netcomm/docs/pubs/index.html

Contains the following:

    MPC8260 PowerQUICC II User's Manual, rev. 0
    MPC8260 PowerQUICC II User's Manual Errata, rev. 0
    MPC8260 Design Checklist