Assembler Coding Notes -

E Assembler Coding Notes

Instruction Mnemonics 611
Operand Addressing Modes 612
Registers 612
Expressions 612

This section describes the conventions used in the Diab Assembler to specify instruction mnemonics and addressing modes.

Instruction Mnemonics

The Diab Assembler supports all PowerPC instructions as described in the PowerPC Microprocessor Family: The Programming Environments manuals, including the simplified mnemonics described there.

Operand Addressing Modes

Registers

This section specifies the valid names for registers. See Register use, p.181 for details on register use.

Registers can be specified in the following ways, in either lower or upper case:

Table E-1 Register names

Register Use/Description
r0 - r31
0 - 31
General purpose registers; can only be used where a general purpose register is expected.
f0 - f31
0 - 31
Floating point registers; can only be used where a floating point register is expected.
cr0 - cr7
0 - 7
Condition code registers; can only be used where a condition code register is expected.
sr0 - sr15
0 - 15
Segment registers; can only be used where a segment register is expected.
1 - 1023
xer (1)
ctr (9)
lr (8)
Special purpose registers; can only be used where a special purpose register is expected. Only the most common register names are shown. Diab Assembler recognizes all special purpose registers for the supported targets.

Register	Use/Description
r0 - r31 0 - 31	General purpose registers; can only be used where a general purpose register is expected.
f0 - f31 0 - 31	Floating point registers; can only be used where a floating point register is expected.
cr0 - cr7 0 - 7	Condition code registers; can only be used where a condition code register is expected.
sr0 - sr15 0 - 15	Segment registers; can only be used where a segment register is expected.
1 - 1023 xer (1) ctr (9) lr (8)	Special purpose registers; can only be used where a special purpose register is expected. Only the most common register names are shown. Diab Assembler recognizes all special purpose registers for the supported targets.

Expressions

See Chapter 19, Assembler Expressions, p.311, for a complete description of valid expressions. There are no limits on the complexity of an expression as long as all the operands are constants. When a label is used in the expression, the assembler will generate a relocation entry so that the linker can patch the instruction with the correct address. See Table F-7, ELF relocation types and examples, p.624 and Table G-8, COFF relocation types, p.638 for a complete list of relocation types.

The following table shows examples of expressions for common addressing modes:

Example	Description
`addis r3,r0,var@ha lwz r3,r3,var@l`	Load r3 with the value pointed to by the 32 bit address of var. var@ha will extract the higher 16 bits and adjust them so that when adding the sign extended lower 16 bits, var@l, the resulting value will be the address of var.
`addis r3,r0,(var+4)@ha lwz r3,(var+4)@l(r3)`	Same as above, but use the address of var plus 4.
`lwz r3,svar@sdarx(r0)`	Load r3 with the value of svar located in one of the Small Data Areas (SDA). There are three 64KB SDAs: One area pointed to by register r13 for regular small data. Usually in the sections .sdata and .sbss. One area pointed to by register r2 for constant small data. Usually in the sections .sdata2. One area located around address 0 (register r0). The assembler will generate the appropriate relocation information and the Diab linker will patch the instruction to use the correct register and the correct offset.
`addis r3,r0,var@sdarx@ha lwz r3,var@sdax@l(r3)`	Load r3 with the value of var by adding a 32 bit offset to one of the base registers described above. This is a way of getting position-independent data for data areas bigger than 64K.