VxWorks BSP Developer's Reference : VxWorks BSP Validation Test Suite
busTas - bus test-and-set test
bspVal options busTas
This module is the Tcl code for the test-and-set test. It verifies the sysBusTas( ) operation between two VxWorks target boards in a common VME backplane. This module is implemented in Tcl and WTX protocols functions. The entire test takes approximately 10 minutes to run. See bspVal.sh for an explanation of options.
If this test is run between two targets using shared memory, make sure the target is configured to include shared memory show routines. To do this, add INCLUDE_SHOW_ROUTINES to config.h of the BSPs or include the component INCLUDE_SM_NET_SHOW, if using project facility.
The script does not reboot the targets. It assumes that the two targets and their respective target servers are up and running.
NOTE: This reference entry lists the most likely reasons for a test's failure. However, it does not list all possible reasons. By default the test assumes that T1 target is the system controller on the common VME backplane. An optional configuration parameter T1_BUS_MASTER can be set to FALSE to override this default configuration. In this case the T2 target is assumed to be the system controller. It is necessary to make sure that T1_BUS_MASTER has the correct value in case targets have to be rebooted before running any test.
The test starts by obtaining two cache-coherent memory locations by calls to cacheDmaMalloc( ) on the master. These two memory locations are used for the semaphore and the access counter. The pkTestRamByte function checks that the addresses returned by cacheDmaMalloc( ) are readable and writable.
Next, the local addresses are used to compute the bus addresses by calling the function sysLocalToBusAdrs( ) on the master. The bus addresses returned by sysLocalToBusAdrs( ) are passed to the slave, which uses the function sysBusToLocalAdrs( ) to get its own local addresses that it must apply to access the semaphore and counter locations on the master's shared memory. The smAdrsFind procedure is called to verify that the counter and semaphore locations are seen by both the master and the slave. The memory locations are then initialized and the test is started by spawning the pkTasTest task on both master and slave. The functions wtxContextCreate( ) and wtxContextResume( ) are used here to spawn and start the tasks. The function pkTasTest( ) uses the semaphore location for mutual exclusion. When the master gets the semaphore, it increments the counter, if it is odd, and runs a busy-wait loop until it finally clears the semaphore. The slave runs the same way except that it increments the counter if it is even. This scheme ensures that the two tasks take turns grabbing the semaphore and incrementing the counter.
The counter is monitored from the script, which takes two readings of the counter one second apart. If the second reading is larger than the first one, the short-term test is successful. After a pause of ten minutes, the two readings are retaken. If the counter is still increasing, the long-term test is successful.
If this test fails, check that the master and slave are both accessing the same two master memory locations. If the master sysLocalToBusAdrs( ) or the slave sysBusToLocalAdrs( ) routines are not functioning properly, the test will not be able to find appropriate slave addresses that access the master memory locations. The master memory locations must be cache-coherent and must be writable. The VME controller chips must be initialized to proper values. For fast target boards, it might be necessary to increase the busy-wait delays given by the T1_TAS_DELAY (T2_TAS_DELAY) macro.
The two tests in this script require two unique cache-coherent memory locations on master that can be accessed by both master and slave. By default, these locations are obtained by calls to cacheDmaMalloc( ) on the master. Alternatively, the macros T1_COUNT_ADRS and/or T1_SEM_ADRS can be changed from the default of "-1" to point to unique shared memory addresses on master. In this case, the user must make sure that these are free cache-coherent memory locations. The ability to explicitly declare these locations is provided for debugging purposes and for boards with hardware limitations. The final validation should leave the macros set to "-1", and allocate the memory dynamically by calling cacheDmaMalloc( ).
Barring serious hardware or software limitations (such as an identifiable VxWorks problem), the target board must pass all tests for the BSP to be validated. Of course, if the VME backplane is not supported by the target board, then this test is not a BSP validation requirement.
- T1_COUNT_ADRS 25
- Address of master's shared counter (optional).
- T1_SEM_ADRS
- Address of master's shared semaphore (optional).
- T1_TAS_DELAY
- Busy delay during TAS on master (optional).
- T2_TAS_DELAY
- Busy delay during TAS on slave (optional).
Output consists of:
BSP VALIDATION TEST ------------------- Target server : t53-160 BSP : mv147 Second target server : t214-2 Second BSP : mv147 Log file : /tmp/bspValidationLog.6425 busTas: short-term TAS test : PASS long-term TAS test : PASS Tests RUN 2 Tests PASSED 2 Tests FAILED 0 Tests SKIPPED 0
bspVal.sh, smLib.tcl, pkLib.c